MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 145

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP
RSP
RTI
RTS
SBC #opr8i
SBC opr8a
SBC opr16a
SBC oprx16,X
SBC oprx8,X
SBC ,X
SBC oprx16,SP
SBC oprx8,SP
SEC
SEI
STA opr8a
STA opr16a
STA oprx16,X
STA oprx8,X
STA ,X
STA oprx16,SP
STA oprx8,SP
STHX opr8a
STHX opr16a
STHX oprx8,SP
STOP
STX opr8a
STX opr16a
STX oprx16,X
STX oprx8,X
STX ,X
STX oprx16,SP
STX oprx8,SP
SUB #opr8i
SUB opr8a
SUB opr16a
SUB oprx16,X
SUB oprx8,X
SUB ,X
SUB oprx16,SP
SUB oprx8,SP
SWI
Source
Form
Rotate Right through
Carry
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Subtract with Carry
Set Carry Bit
Set Interrupt Mask Bit
Store Accumulator in
Memory
Store H:X (Index Reg.)
Enable Interrupts:
Stop Processing
Refer to MCU
Documentation
Store X (Low 8 Bits of
Index Register)
in Memory
Subtract
Software Interrupt
Operation
Table 8-2. HCS08 Instruction Set Summary (Sheet 6 of 7)
MC9S08GB60A Data Sheet, Rev. 2
Push (CCR); SP ← (SP) – 0x0001
Push (PCH); SP ← (SP) – 0x0001
PCH ← Interrupt Vector High Byte
SP ← (SP) + 0x0001; Pull (CCR)
Push (PCL); SP ← (SP) – 0x0001
SP ← (SP) + 0x0001; Pull (PCH)
PCL ← Interrupt Vector Low Byte
SP ← (SP) + 0x0001; Pull (PCL)
SP ← SP + 0x0001; Pull (PCH)
SP ← SP + 0x0001; Pull (PCL)
Push (X); SP ← (SP) – 0x0001
Push (A); SP ← (SP) – 0x0001
SP ← (SP) + 0x0001; Pull (A)
SP ← (SP) + 0x0001; Pull (X)
I bit ← 0; Stop Processing
(M:M + 0x0001) ← (H:X)
(High Byte Not Affected)
PC ← (PC) + 0x0001
b7
A ← (A) – (M) – (C)
Description
A ← (A) – (M)
SP ← 0xFF
M ← (A)
M ← (X)
C ← 1
I ← 1;
I ← 1
b0
C
V H I N Z C
– – – – – –
– – – – – –
– – – – – 1
– – 1 – – –
0 – –
0 – –
– – 0 – – –
0 – –
– – 1 – – –
– –
– –
– –
Chapter 8 Central Processor Unit (S08CPUV2)
on CCR
Effect
–
–
–
DIR
INH
INH
IX1
IX
SP1
INH
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
INH
INH
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
EXT
SP1
INH
DIR
EXT
IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
INH
9EDF
9ED2
9EE2
9ED7
9EE7
9EFF
9EEF
9ED0
9EE0
9E66
CF
DF
9C
C2
D2
C7
D7
BF
EF
C0
D0
A2
B2
E2
9B
B7
E7
8E
FF
A0
B0
E0
36
46
56
66
76
80
81
F2
99
F7
35
96
F0
83
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
hh ll
ee ff
ff
ee ff
ff
dd
hh ll
ff
dd
hh ll
ee ff
ff
ee ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
2+
11
5
1
1
5
4
6
1
9
6
2
3
4
4
3
3
5
4
1
1
3
4
4
3
2
5
4
4
5
5
3
4
4
3
2
5
4
2
3
4
4
3
3
5
4
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