RG82845G S L66F Intel, RG82845G S L66F Datasheet - Page 80

• Manufacturer Part Number: RG82845G S L66F
• Manufacturer: Intel

Specifications of RG82845G S L66F

• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.5.2.3
80
PCICMD1—PCI Command Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved.
Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0.
SERR Message Enable (SERRE). This bit is a global enable bit for Device 1 SERR messaging. The
GMCH communicates the SERR# condition by sending an SERR message to the ICH. If this bit is
set to a 1, the GMCH is enabled to generate SERR messages over HI for specific Device 1 error
conditions that are individually enabled in the BCTRL1 register. The error status is reported in the
PCISTS1 register. If SERRE1 is reset to 0, then the SERR message is not generated by the GMCH
for Device 1.
Address/Data Stepping (ADSTEP). Hardwired to 0. Address/data stepping is not implemented in
the GMCH.
Parity Error Enable (PERRE). Hardwired to 0. Parity checking is not supported on the primary side
of this device.
Reserved.
Memory Write and Invalidate Enable (MWIE). Hardwired to 0.
Special Cycle Enable (SCE). Hardwired to 0.
Bus Master Enable (BME).
0 = Disable (Default). AGP Master initiated Frame# cycles are ignored by the GMCH. The result is a
1 = AGP master initiated Frame# cycles are accepted by the GMCH if they hit a valid address
Memory Access Enable (MAE).
0 = Disable. All of Device 1’s memory space is disabled.
1 = Enable. This bit must be set to 1 to enable the Memory and Pre-fetchable memory address
IO Access Enable (IOAE).
0 = Disable. All of Device 1’s I/O space is disabled.
1 = Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and
master abort. Ignoring incoming cycles on the secondary side of the PCI-to-PCI bridge
effectively disabled the bus master on the primary side.
decode range. This bit has no affect on AGP Master originated SBA or PIPE# cycles.
ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
IOLIMIT1 registers.
04–05h
0000h
RO, R/W
16 bits
Intel
Description
®
82845G/82845GL/82845GV GMCH Datasheet