RG82845G S L66F Intel, RG82845G S L66F Datasheet - Page 29

• Manufacturer Part Number: RG82845G S L66F
• Manufacturer: Intel

Specifications of RG82845G S L66F

• Lead Free Status / RoHS Status: Not Compliant

2.4
2.4.1
2.4.2
Intel
®
82845G/82845GL/82845GV GMCH Datasheet
Note: The above table contains two mechanisms to queue requests by the AGP master. Note that the
AGP Interface Signals
AGP Addressing Signals
master can only use one mechanism. When PIPE# is used to queue addresses, the master is not
allowed to queue addresses using the sideband (SB) bus. During configuration time, if the master
indicates that it can use either mechanism, the configuration software indicates which mechanism
the master will use. Once this choice has been made, the master continues to use the mechanism
selected until the master is reset (and reprogrammed) to use the other mode. This change of modes
is not a dynamic mechanism but rather a static decision when the device is first being configured
after reset.
AGP Flow Control Signals
GPIPE#
GSBA[7:0]
GRBF#
GWBF#
Signal Name
Signal Name
Type
AGP
AGP
Type
AGP
AGP
I
I
I
I
Pipelined Read: This signal is asserted by the current master to indicate a full
width address is to be queued by the target. The master queues one request each
rising clock edge while GPIPE# is asserted. When GPIPE# is deasserted, no new
requests are queued across the GAD bus.
GPIPE# is a sustained tri-state signal from the master (graphics controller) and is
an input to the GMCH.
Sideband Address: This bus provides an additional bus to pass addresses and
commands to the GMCH from the AGP master.
Read Buffer Full: This signal indicates if the master is ready to accept previously
requested low priority read data. When GRBF# is asserted, the GMCH is not
allowed to return low priority read data to the AGP master. GRBF# is only
sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data, it is not required to
implement this signal.
Write Buffer Full: This signal indicates if the master is ready to accept fast write
data from the GMCH. When GWBF# is asserted, the GMCH is not allowed to
drive fast write data to the AGP master. GWBF# is only sampled at the beginning
of a cycle.
If the AGP master is always ready to accept fast write data, it is not required to
implement this signal.
Description
Description
Signal Description
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