RG82845G S L66F Intel, RG82845G S L66F Datasheet - Page 116

• Manufacturer Part Number: RG82845G S L66F
• Manufacturer: Intel

Specifications of RG82845G S L66F

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
116
Table 4-8. PCI Commands Supported by GMCH When Acting As an AGP/PCI_B Initiator
Memory Read Line, and Memory Read Multiple:
by the GMCH. The GMCH issues two snoops (a snoop followed by a snoop-ahead) on the host bus
and releases the processor bus for other traffic. When the first DWord of the first cache line is
delivered and GFRAME# is still asserted, the GMCH issues another snoop-ahead on the host bus.
This allows the GMCH to continuously supply data during memory read line and memory read
multiple bursts. When the transaction terminates, there may be a minimum of 2 cache lines and a
maximum of 2 cache lines plus 7 DWords buffered. Subsequent memory reads hitting the buffers
will return data from the buffer.
Memory Write and Memory Write and Invalidate:
processed identically. The GMCH supports data streaming for PCI-to-DRAM writes based on its
ability to buffer up to 128 bytes (16 QWords) of data before a snoop cycle must be completed on
the host bus. The GMCH is typically able to support longer write bursts, with the maximum length
dependent upon concurrent host bus traffic during PCI-DRAM write data streaming.
Fast Back-to-Back Transactions:
from a PCI initiator. As a PCI initiator, the GMCH is responsible for translating host cycles to
AGP/PCI_B cycles. The GMCH also transfers hub interface to AGP/PCI_B write cycles.
shows all the cycles that need to be translated.
(Sheet 1 of 2)
Source Bus: Host
Deferred Reply
Interrupt Acknowledge
Special Cycle
Branch Trace Message
I/O Read
I/O Write
I/O Read to 0CFCh
I/O Write to 0CFCh
Memory Read (Code or
Data)
Memory Read
Invalidate
Memory Write
Locked Access
Reserved Encodings
Source Bus
Command
Don’t Care
Length ≤ 8 Bytes
Shutdown
Halt
Stop Clock Grant
All Other Combinations
None
Length ≤ 8 Bytes up to 4 BEx Asserted
Length ≤ 8 Bytes up to 4 BEx Asserted
Length ≤ 8 Bytes up to 4 BEx Asserted
Length ≤ 8 Bytes up to 4 BEx Asserted
Length < 8 Bytes without All BEs Asserted
Length = 8 Bytes with All BEs Asserted
Length = 16 Bytes
Length = 32 Bytes Code Only
Length < 8 Bytes without All BEs Asserted
Length = 16 Bytes
Length = 32 Bytes
All Combinations
All Combinations
Other Encoded Information
The GMCH, as a target, supports fast back-to-back cycles
Intel
®
82845G/82845GL/82845GV GMCH Datasheet
These commands are treated identically
These commands are aliased and
Configuration Read
Configuration Write
PCI_B Command
Unlocked Access
Corresponding
Memory Read
Memory Read
Memory Read
Memory Write
Memory Write
I/O Read
I/O Write
None
None
None
None
None
None
None
None
None
None
GMCH Host Bridge
1
As Applicable
GC/BE[3:0]#
Encoding
Table 4-8
0010
0011
1010
1011
0110
1110
1110
0111
0111
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A