RG82845G S L66F Intel, RG82845G S L66F Datasheet - Page 100

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RG82845G S L66F

Manufacturer Part Number
RG82845G S L66F
Description
Manufacturer
Intel
Datasheet

Specifications of RG82845G S L66F

Lead Free Status / RoHS Status
Not Compliant
Register Description
3.5.3.17
3.5.3.18
3.5.3.19
3.5.3.20
100
INTRPIN—Interrupt Pin Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
MINGNT—Minimum Grant Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
MAXLAT—Maximum Latency Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
PMCAPID—Power Management Capabilities ID Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
15:8
Bit
7:0
Bit
7:0
Bit
7:0
Bit
7:0
Interrupt Pin. As a single function device, the IGD specifies INTA# as its interrupt pin.
01h=INTA#.
Minimum Grant Value. The IGD does not burst as a PCI compliant master.
Bits[7:0]=00h.
Maximum Latency Value. Bits[7:0]=00h. The IGD has no specific requirements for how often it
needs to access the PCI bus.
NEXT_PTR. This contains a pointer to next item in capabilities list. This is the final capability in the
list and must be set to 00h.
CAP_ID. SIG defines this ID is 01h for power management.
3Dh
01h
RO
8 bits
3Eh
00h
RO
8 bits
3Fh
00h
RO
8 bits
D0h−D1h
0001h
RO
16 bits
Intel
Description
Description
Description
Description
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