RG82845G S L66F Intel, RG82845G S L66F Datasheet
RG82845G S L66F
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RG82845G S L66F Summary of contents
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... Intel 845G/845GL/845GV Chipset Datasheet ® Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) October 2002 Document Number: 290746-002 ...
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... C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...
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... Intel 82845G/82845GL/82845GV GMCH ...........................................................................................................13 ® 845G Chipset System Overview ..........................................................15 Host Interface....................................................................................17 System Memory Interface .................................................................17 Hub Interface ....................................................................................17 Multiplexed AGP and Intel Graphics Overview............................................................................18 Display Interfaces .............................................................................19 ..............................................................................................21 DDR SDRAM Interface .....................................................................25 SDR SDRAM Interface .....................................................................26 AGP Addressing Signals...................................................................29 AGP Flow Control Signals ................................................................29 AGP Status Signals ..........................................................................30 AGP Strobes .....................................................................................30 PCI Signals– ...
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... PCISTS1—PCI Status Register (Device 1)....................... 81 3.5.2.5 RID1—Revision Identification Register (Device 1) ............ 82 3.5.2.6 SUBC1—Sub-Class Code Register (Device 1) ................. 82 3.5.2.7 BCC1—Base Class Code Register (Device 1).................. 82 3.5.2.8 MLT1—Master Latency Timer Register (Device 1) ........... 83 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... Functional Description 4.1 Processor System Bus.................................................................................105 ® Intel 82845G/82845GL/82845GV GMCH 3.5.2.9 HDR1—Header Type Register (Device 1).........................83 3.5.2.10 PBUSN1—Primary Bus Number Register (Device 1) .......83 3.5.2.11 SBUSN1—Secondary Bus Number Register (Device 1)...84 3.5.2.12 SUBUSN1—Subordinate Bus Number Register (Device 1).. ...
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... Digital Display Channels – DVOB and DVOC................. 133 4.5.2.2 Synchronous Display....................................................... 135 Power Management Support Overview .......................................... 136 Processor Power State Control....................................................... 136 Sleep State Control......................................................................... 136 Graphics Adapter State Control ...................................................... 136 Monitor State Control ...................................................................... 137 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... DAC Reference and Output Specifications.....................................154 DAC AC Characteristics..................................................................154 ® 82845G GMCH Ballout ......................................................................155 .............................................................................................................173 .................................................................181 ® ® 82845G and Intel 82845GL/82845GV Signal Differences ...............182 Functional Straps (82845GL only) ..................................................182 ® ® 82845G and Intel 82845GL/82845GV Register Differences............183 DRAM Controller/Host-Hub Interface Device Registers (Device 0) 183 9 ...
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... Figures 1-1 Intel 2-1 Intel 2-2 Intel 2-3 Full and Warm Reset Waveforms .................................................................. 39 3-1 Conceptual Intel 3-2 Configuration Mechanism Type 0 Configuration Address to PCI Address Mapping ......................................................................................................... 45 3-3 Configuration Mechanism Type 1 Configuration Address to PCI Address Mapping ......................................................................................................... 46 3-4 PAM Register Attributes ................................................................................ 65 4-1 Intel 4-2 ...
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... XOR Chains 3, 4, and 5 ...............................................................................176 8-4 XOR Chains 6, 7, and 8 ...............................................................................178 8-5 XOR Chains Excluded Pins .........................................................................180 9-1 Intel ® Intel 82845G/82845GL/82845GV GMCH ® 82845G GMCH Package Thermal Resistance ..................................147 ® 82845G GMCH Ballout by Ball Number.............................................158 ® 82845G GMCH Ballout by Signal Name ............................................164 ® ...
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... Revision History Revision -001 Initial release -002 Added 82845GV information (see appendix A for details) 10 Changes ® Intel 82845G/82845GL/82845GV GMCH Date May 2002 October 2002 Datasheet ...
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... Supports a single 1.5 V Accelerated Graphics Port Interface, Specification 2.0-compliant device — Supports 1X/2X/4X data transfers and 2X/4X Fast Writes — 32-deep AGP request queue — AGP signals muxed with two Intel Supports ADD cards ® Intel 82845G/82845GL/82845GV GMCH Integrated Graphics I — ...
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... This page is intentionally left blank ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... MHz/400 MHz frequencies and Hyper-Threading Technology. — 82845GL supports 400 MHz only and does not support Hyper-Threading Technology. • AGP Interface — 82845G supports AGP. The AGP interface signals are multiplexed with the Intel interface signals. — 82845GL and 82845GV do not support AGP. Chapter 1 through ...
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... JEDEC Double Data Rate (DDR) SDRAM Specification ® Intel PC SDRAM Specification Accelerated Graphics Port Interface Specification, Revision 2.0 Digital Visual Interface (DVI) Specification, Revision 1.0 NOTE: For additional related documents, refer to the Intel ® Intel 845G/845GL/845GV Chipset Platform Design Guide. 14 Description ® ...
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... AGP. The IGD has 3D, 2D, and video capabilities. The IGD also has two multiplexed Intel DVO ports to support DVO devices. The GMCH’s AGP interface supports 1X/2X/4X AGP data transfers and 2X/4X AGP Fast Writes, as defined in the Accelerated Graphics Port Interface Specification, Revision 2 ...
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... Introduction ® Figure 1-1. Intel 845G Chipset System Block Diagram AGP 4x Or ® 2 Intel DVO Ports 4 IDE Devices UltraATA/100 6 USB Ports, 3UHCI, EHCI AC '97 Codec(s) (optional) LAN Connect Debug Port GPIO 16 Processor System Bus 400/533 MHz VGA 845G Chipset Intel ® ...
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... CPC) accesses. 1.4.3 Hub Interface The hub interface connects the GMCH to the ICH4. Most communication between the GMCH and the ICH4 occurs over this interface. The hub interface runs at 66 MHz/266 MB/s and is powered with 1.5 V. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Introduction 17 ...
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... High bandwidth access to data is provided through the system memory port. The GMCH can access graphics data located in system memory at 1.0 GB/s (SDR PC133), 1.6 GB/s (DDR200) or 2.2 GB/s (DDR266). The GMCH uses Intel’s Direct Memory Execution model to fetch textures from system memory. The GMCH includes a cache controller to avoid frequent memory fetches of recently used texture data ...
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... The GMCH is compliant with the Digital Visual Interface (DVI) Specification, Revision 1.0 (www.ddwg.org/register/download.htm). When combined with a DVI-compliant external device and connector, the GMCH has a high-speed interface to a digital display (e.g., flat panel or digital CRT). ® Intel 82845G/82845GL/82845GV GMCH Datasheet Introduction • 2D Graphics — Optimized 256-bit BLT Engine — ...
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... Introduction 20 This page is intentionally left blank. ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... GMCH host bridge. All processor control signals follow normal convention indicates an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Signal Description 2 21 ...
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... Signal Description ® Figure 2-1. Intel 82845G GMCH Interface Block Diagram HA_[31:3]# HD_[63:0]# DEFER# HLOCK# HREQ_[4:0]# HTRDY# RS_[2:0]# CPURST# BREQ0# DINV_[3:0]# HADSTB_[1:0]# HDSTB_P[3:0]#, HDSTB_N[3:0]# SCS_[3:0]# SMAA_[12:0], SMAB_[5,4,2,1] SBA_[1:0] SDQ_[63:0] SDM_[7:0] SDQS_[8:0] SCKE_[3:0] SCMDCLK_[5:0] SCMDCLK_[5:0]# SRCVEN_OUT# SRCVEN_IN# SCS_[7:0]# SMAA_[12:0] SBA_[1:0] SDQ_[63:0] SDM_[7:0] ...
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... HCLKs. BREQ0# is terminated high (pulled up) after the hold time requirement has been satisfied. O CPU Reset: The CPURST# pin is an output from the GMCH. The GMCH asserts CPURST# while RSTIN# (PCIRST# from Intel for approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the processors to begin execution in a known state. I/O Data Bus Busy: This signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle ...
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... Retry response 010 = Deferred response 011 = Reserved (not driven by GMCH) 100 = Hard Failure (not driven by GMCH) 101 = No data response 110 = Implicit Writeback 111 = Normal data response ® Intel 82845G/82845GL/82845GV GMCH Datasheet Description Data Bits HD_[63:48]#, DINV_3# HD_[47:32]#, DINV_2# HD_[31:16]#, DINV_1# HD_[15:0]#, DINV_0# ...
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... SDQ_[63:0] SDM_[7:0] SDQS_[7:0] SCKE_[3:0] SRCVEN_OUT# SRCVEN_IN# ® Intel 82845G/82845GL/82845GV GMCH Datasheet Type O Differential DDR Clock: SCMDCLK and SCMDCLK# pairs are differential SSTL_2 clock outputs. The crossing of the positive edge of SCMDCLK and the negative edge of SCMDCLK# is used to sample the address and control signals on the SDRAM ...
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... SDQ_63 AJ36 SWE# AK14 SCS_4# AK16 SCS_0# AK18 SCMDCLK_5 SMAA_0 AK20 SMAA_5 AK22 SRCVEN_OUT# AK24 SBA_0 AK26 ® Intel 82845G/82845GL/82845GV GMCH Datasheet Description SDR Ball Name Ball # SWE# SCKE_3 AP29 SDQ_5 SDQ_1 AP3 SDQ_43 SDQ_54 AP30 SCS_1# SCS_6# AP31 SDQ_52 SDQ_24 ...
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... SMAA_8 SMAB_4 SDQ_4 SCMDCLK_3# SMAB_2 SMAA_1 SBA_0 SCAS# SCS_3# SCMDCLK_5# SDQ_56 SDQ_0 SCMDCLK_4# SDQ_16 SCMDCLK_1# SDM_2 ® Intel 82845G/82845GL/82845GV GMCH Datasheet SDR Ball Name Ball # DDR Ball Name SCKE_0 AK28 SCS_3# AK30 SDQ_31 AK34 SDQ_30 AK35 SCMDCLK_4 SDQ_62 AK36 SCAS# AL13 ...
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... Hub Interface Strobe: HI_STBS is one of two differential strobe signals used to transmit or receive packet data over the hub Interface. Hub Interface Strobe Complement: HI_STBF is one of two differential strobe signals used to transmit or receive packet data over the hub Interface. ® Intel 82845G/82845GL/82845GV GMCH Datasheet SDR Ball Name Ball # SDQS_5 ...
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... GRBF# AGP GWBF# AGP ® Intel 82845G/82845GL/82845GV GMCH Datasheet Pipelined Read: This signal is asserted by the current master to indicate a full width address queued by the target. The master queues one request each rising clock edge while GPIPE# is asserted. When GPIPE# is deasserted, no new requests are queued across the GAD bus. ...
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... Sideband Strobe: This signal provides timing for 2X and 4X clocked data on the I GSBA[7:0] bus driven by the AGP master after the system has been configured for clocked sideband address delivery. I Sideband Strobe Complement: GSBSTB# is the differential complement to the GSBSTB signal used to provide timing for 4X clocked data. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Description Description ...
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... The AGP agent will also typically use PCIRST# provided by the ICH4 as an input to reset its internal logic. 2. The LOCK# signal is not supported on the AGP Interface (even for PCI operations). 3. The PERR# and SERR# signals are not supported on the AGP interface. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Frame: GFRAME output from the GMCH during Fast Writes. AGP Initiator Ready: GIRDY# indicates the AGP compliant master is ready to provide all write data for the current transaction ...
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... O DVOB_CLKOUT0=DVOB_CLK and DVOB_CLKOUT1=DVOB_CLK#. Care AGP should be taken to be sure that DVOB_CLK is connected to the primary clock ® receiver of the Intel DVO device. O DVOB Data: This data bus is used to drive 12-bit pixel data on each edge of AGP DVOB_CLK(#). This provides 24 bits of data per clock. ...
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... MI2C_CLK MI2C_DATA MDVI_CLK MDVI_DATA MDDC_CLK MDDC_DATA ADDID[7:0] ® Intel 82845G/82845GL/82845GV GMCH Datasheet Type I DVOBC Interrupt: This signal may be used as an interrupt input for either of AGP the multiplexed DVO devices. TV Field and Flat Panel Stall Signal: This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. ...
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... DVOC_VSYNC GC/BE_1# DVOC_BLANK# GAD_13 DVOBC_INTR# GAD_14 DVOC_FLDSTL AGP RCOMP ADDID[7:0] GIRDY# MDVI DATA GDEVSEL# MDDC CLK GTRDY# MDDC DATA ® Intel 82845G/82845GL/82845GV GMCH Datasheet AGP Signal Name GAD_19 GAD_20 GAD_21 GAD_22 GAD_23 GC/BE_3# GAD_25 GAD_24 GAD_27 GAD_26 GAD_29 GAD_28 GADSTB_1 GADSTB_1# ...
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... DAC. The DAC is designed for a 37.5 Ω equivalent load on each signal (e.g., 75 Ω resistor on the board, in parallel with a 75 Ω CRT load). BLUE# Analog Output: This signal is a truly differential analog video output from the internal color palette DAC. Refer to the Intel O ® 478-Pin Package and Intel 845G/845GL/845GV Chipset Platform Design Guide for routing recommendations ...
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... Panel and DAC. Reset In: When asserted, this signal asynchronously resets the GMCH logic. This signal is connected to the PCIRST# output of the Intel and bi-directional signals will also tri-state compliant to PCI Local Bus Specification, Revision 2.0 and PCI Local Bus Specification, Revision 2.1. ...
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... VCC for 1.5 V core. VSS GND supply. VCCAGP VCC for AGP – 1.5 V. Analog Vcc for the Host PLL – 1.5 V. This supply requires special filtering. Refer to the Intel VCCA_FSB Pentium Design Guide for details. VTTFSB VTT supply for PSB, having a range of 1.15 V–1.75 V. ...
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... MHz when PSBSEL and runs at 533 MHz when PSBSEL Memory Configuration Select: This pin selects the SDR or DDR board configuration. The pin should be unconnected for DDR configuration. For SDR configuration, a pull-down resistor is required. Refer to the Intel ® Processor in 478-Pin Package and Intel Design Guide for details ...
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... RSTIN#) is asserted and PWROK is also asserted. The following table describes the reset states. Reset State Full Reset Warm Reset Does Not Occur Normal Operation ® Intel 82845G/82845GL/82845GV GMCH Datasheet 1 ms min Write on CF9h 1 ms min Unknown Full Reset Warm Reset ...
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... Signal Description 40 This page is intentionally left blank. ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... Read/Write Once. A register (bit) with this attribute can be written only once after power up. R/WO After the first write, the register (bit) becomes read only. L Lock. A register bit with this attribute becomes read only after a lock bit is set. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Register Description Description 3 41 ...
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... Registers (“Reserved” registers can be 8-, 16-, or 32-bits in size). Writes to “Reserved” registers have no effect on the GMCH. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “ Intel Reserved ” registers may cause system failure. Reads to “Intel Reserved” ...
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... PCI #0 while the secondary side is the standard PCI expansion bus. Note: A physical PCI bus #0 does not exist and that the hub interface and the internal devices in the GMCH and ICH4 logically constitute PCI Bus #0 to configuration software. Figure 3-1. Conceptual Intel 3.3 Routing Configuration Accesses The GMCH supports two bus interfaces: Hub interface and AGP/PCI ...
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... Therefore, the Primary Bus Number register is hardwired to 0. The “virtual” PCI-to-PCI bridge entity converts Type #1 PCI Bus Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the AGP/PCI_B interface. Type 1 configuration cycles on PCI Bus #0 that 44 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... Subordinate Bus Number register the configuration cycle is targeting a PCI bus downstream of the targeted interface. The GMCH will generate a Type 1 PCI configuration cycle on PCI_B/AGP. The address bits will be mapped as described in Figure ® Intel 82845G/82845GL/82845GV GMCH Datasheet CONFIG_ADDRESS ...
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... Number, Function Number, and Register Number for which a subsequent configuration access is intended Reserved Bus Number Device Number 1 Function Number 0 Bus Number Device Number Function Number 0CF8h Accessed as a DWord 00000000h R/W 32 bits ® Intel 82845G/82845GL/82845GV GMCH Datasheet Reg. Index Reg. Index ...
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... Reserved. These bits are read only and have a value of 0. Bus Number. When the Bus Number is programmed to 00h the target of the Configuration Cycle is a hub interface agent (GMCH, Intel interface if the Bus Number is programmed to 00h and the GMCH is not the target. ...
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... Intel Reserved Subsystem Vendor Identification Subsystem Identification Intel Reserved Capabilities Pointer Intel Reserved AGP Miscellaneous Configuration Graphics Control Intel Reserved DRAM Row Boundary (4 registers) Intel Reserved DRAM Row Attribute (4 registers) Intel Reserved DRAM Timing Register DRAM Controller Mode Intel Reserved ® ...
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... Intel Reserved Aperture Translation Table AGP MTT Control R AGP Low Priority Transaction Timer Intel Reserved GMCH Configuration Error Status Error Command SMI Command SCI Command Intel Reserved Scratchpad Data Intel Reserved Capability Identification Intel Reserved Register Description Default Value Access 00h RO, R/W ...
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... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit Vendor Identification (VID). This register field contains the PCI standard identification for Intel, 15:0 8086h. — ...
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... Bus Master Enable (BME)—RO. Hardwired to 1. The GMCH is always enabled as a master on the 2 hub interface. Memory Access Enable (MAE)—RO. Hardwired to 1. Not implemented. The GMCH always allows 1 access to main memory. 0 I/O Access Enable (IOAE)—RO. Hardwired to 0. Not implemented. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 04–05h 0006h RO, R/W 16 bits Description Register Description 51 ...
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... A list of new capabilities is accessed via 4 CAPPTR register (offset 34h). The CAPPTR register contains an offset pointing to the start address within configuration space of this device where the AGP Capability standard register resides. 3:0 Reserved. 52 06–07h 0090h RO, R/WC 16 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... This register contains the Base Class Code of the GMCH Device 0. Bit Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the GMCH. 7:0 06h = Bridge device. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 08h See table below RO 8 bits Description ...
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... This register identifies the header layout of the configuration space. No physical register exists at this location. Bit PCI Header (HDR). This field always returns 0 to indicate that the GMCH is a single function device 7:0 with standard header layout. 54 0Dh 00h RO 8 bits Description 0Eh 00h RO 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... Local Bus Specification, Revision 2.1 for base address registers. Memory Space Indicator (MSPACE)—RO. Hardwired to 0. This identifies the aperture range memory range as per the PCI Local Bus Specification, Revision 2.1 for base address registers. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 10–13h 00000008h RO, R/W ...
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... Pointer Address. This field provides an address that is the offset of the first capability ID register 7:0 block. For the GMCH, the first capability is the Product-Specific Capability that is located at offset E4h. 56 2C–2Dh 0000h R/W-Once 16 bits Description 2E–2Fh 0000h R/W-Once 16 bits Description 34h E4h RO 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... SDRAM has been initialized Disable. (Default). This field must be set after the system is fully configured in order to enable aperture accesses Enable. 0 Reserved. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 51h 00h R/W 8 bits Description Register Description ...
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... Disable. The IGD does Not claim VGA cycles (Mem and IO), and the Sub-Class Code field within Device 2 Class Code register is 80h. Graphics Memory Size (GMEMS)—R/W. This bit controls GMADR register in Device 128 MB (Default Device 0) 52h 0000_1000b R/W 8 bits Description 1 . ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... TSEG pre-allocated from Graphics Local Memory pre-allocated from 03E80000h to 03F7FFFFh VGA Memory and I/O Space Decode Priority 1. Integrated Graphics Device (IGD), Device 2. 2. PCI-to-PCI bridge, Device 1. 3. Hub Interface. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Register Description 00000000h to 03E7FFFFh 03F80000h to 03FFFFFFh 03F80000h to 03FFFFFFh 59 ...
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... DRAM Row Boundary Address. This 8-bit value defines the upper and lower addresses for each 7:0 SDRAM row. This 8-bit value is compared against a set of address lines to determine the upper address limit of a particular row. 60 60–63h (64h–6Fh Reserved) 01h Read/Write 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... KB Others = Reserved 3 Reserved. Row Attribute for Even-numbered Row. This field defines the page size of the corresponding row. 000 = 2 KB 001 = 4 KB 2:0 010 = 8 KB 011 = 16 KB Others = Reserved ® Intel 82845G/82845GL/82845GV GMCH Datasheet 70–71h (72–77h Reserved) 00h R/W 8 bits ...
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... DRAM Clocks 3 DRAM Clocks 11 = Reserved DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row Intel Reserved 1 DRAM Clocks DRAM Clocks 11 = Reserved 62 78–7Bh ...
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... The entry into power-down mode is performed by de-activation of CKE. The exit is performed by 28 activation of CKE Disable Enable. 27:10 Intel Reserved. Refresh Mode Select (RMS)—R/W. This field determines at what rate refreshes will be executed. 000 = Reserved 001 = Refresh enabled. Refresh interval 15.6 µs 9:7 010 = Refresh enabled. Refresh interval 7.8 µs 011 = Refresh enabled. Refresh interval 64 µ ...
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... Register Description Bit 3:1 Intel Reserved. DRAM Type (DT)—RO. This bit indicates SDRAM type Single Data Rate (SDR) SDRAM 1 = Double Data Rate (DDR) SDRAM 3.5.1.20 PAM[0:6]—Programmable Attribute Map Registers (Device 0) Address Offset: Default Value: Attribute: Size: The GMCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 768-KB to 1-MB address range ...
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... PAM2[7:4] R PAM3[3:0] R PAM3[7:4] R PAM4[3:0] R PAM4[7:4] R PAM5[3:0] R PAM5[7:4] R PAM6[3:0] R PAM6[7:4] R For details on overall system address mapping scheme, refer to ® Intel 82845G/82845GL/82845GV GMCH Datasheet and Table 3-2 show the PAM registers and the associated attribute bits. PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 ...
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... PAM Control registers as defined by System BIOS Area (F0000h–FFFFFh) This area is a single, 64-KB segment, which can be assigned with different attributes via the PAM Control registers as defined by 66 Table 3-2. Table 3-2. Table 3-2. ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... SMM space. SMM SDRAM is not remapped simply made visible if the conditions are right to 2:0 access SMM space, otherwise the access is forwarded to the hub interface. Since the GMCH supports only the SMM space between A0000h and BFFFFh, this field is hardwired to 010. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 97h 00h R/W, RO ...
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... Enable. Enabling of SMRAM memory for Extended SMRAM space only. When 0 G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. NOTE: Once D_LCK is set, this bit becomes read only. 68 9Eh 38h R/W, R/WC, RO bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... Data Rate Support (RATE). After reset the GMCH reports its data transfer rate capability. Bit 0 2:0 identifies if the AGP device supports 1X data transfer mode, bit 1 identifies if AGP device supports 2X data transfer mode, bit 2 identifies if AGP device supports 4X data transfer ® Intel 82845G/82845GL/82845GV GMCH Datasheet A0–A3h 00200002h RO ...
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... This register enables additional control of the AGP interface. Bit 31:8 Intel Reserved. GTLB Enable (GTLBEN =Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry. 1 =Enable. Normal operations of the Graphics Translation Lookaside Buffer. 6:0 Intel Reserved. 70 A8–ABh 00000000h RO, R/W 32 bits Description B0–B3h 00000000h ...
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... Aperture Translation Table Base (TTABLE). This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main 31:12 memory. NOTE: This field should be modified only when the GTLB has been disabled. 11:0 Reserved. ® Intel 82845G/82845GL/82845GV GMCH Datasheet B4h 00h RO, R/W 8 bits Description B8–BBh ...
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... MHz clock granularity) allotted to the current low priority AGP transaction data transfer state). 2:0 Reserved. 72 BCh 10h Read Only, Read/Write 8 bits Description BDh 10h R/W 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
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... System Memory frequency is set to 133 MHz (SDR133, DDR266) 11: System Memory frequency is set to 100 MHz (DDR200) (Default) NOTE: 1. When writing a new value to this bit, a warm reset through the Intel before the bit becomes effective. This must be enforced by BIOS/SW. However, changing this bit in SW requires a “warm reset” 9:6 Intel Reserved ...
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... AGP access was attempted outside of the graphics aperture and either to the 640 KB –1 MB range or above the top of memory. Invalid Graphics Aperture Translation Table Entry (ITTEF invalid translation table entry was returned in response to an AGP access to the graphics aperture. 1:0 Intel Reserved. 74 C8–C9h 0000h R/WC 16 bits Description ® ...
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... SERR on Invalid Translation Table Entry (ITTEF Disable. Reporting of this condition is disabled Enable. GMCH generates an SERR special cycle over HI when an invalid translation table entry was returned in response to an AGP access to the graphics aperture. 1:0 Intel Reserved. ® Intel 82845G/82845GL/82845GV GMCH Datasheet CA–CBh 0000h ...
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... Address Offset: Default Value: Access: Size: This register enables various errors to generate a SMI message via the hub interface. Bit 15:0 Intel Reserved. 3.5.1.36 SCICMD—SCI Command Register (Device 0) Address Offset: Default Value: Access: Size: This register enables various errors to generate a SMI message via the hub interface. ...
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... Identifier Register (ACAPID). If AGP is disabled (IGDIS = 0), since this is the last pointer in the device set to 00h signifying the end of the capabilities linked list. CAP_ID. This field has the value 09h to identify the CAP_ID assigned by the PCI SIG for Vendor 7:0 Dependent CAP_PTR. ® Intel 82845G/82845GL/82845GV GMCH Datasheet E4h–E8h 0x_x105_A009h RO 40 bits ...
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... Secondary Status Memory Base Address Memory Limit Address Prefetchable Memory Base Limit Address Prefetchable Memory Limit Address — Intel Reserved Bridge Control Error Command — Intel Reserved ® Intel 82845G/82845GL/82845GV GMCH Datasheet Table 3-3 provides the Default Value Access 8086h RO 2561h ...
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... Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit Vendor Identification Device 1 (VID1). This register field contains the PCI standard identification for 15:0 Intel, 8086h. 3.5.2.2 DID1—Device Identification Register (Device 1) Address Offset: Default Value: ...
Page 80
... MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers. IO Access Enable (IOAE Disable. All of Device 1’s I/O space is disabled Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers. 80 04–05h 0000h RO, R/W 16 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 81
... Fast Back-to-Back (FB2B)—RO. Hardwired to 1. This indicates that the AGP/PCI_B interface 7 always supports fast back to back writes. 6 Reserved. 5 66/60MHz Capability (CAP66)—RO. Hardwired to 1. The AGP/PCI bus is 66 MHz capable. 4:0 Reserved. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 06–07h 00A0h RO, R/WC 16 bits Description Register Description 81 ...
Page 82
... Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the GMCH Device 1. 7:0 06h = Bridge device. 82 08h see table below RO 8 bits Description 0Ah 04h RO 8 bits Description 0Bh 06h RO 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 83
... Primary Bus Number (BUSN). Configuration software typically programs this field with the number 7:0 of the bus on the primary side of the bridge. Since Device internal device and its primary bus is always 0, these bits are read only and are hardwired to 0. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 0Dh 00h RO, R/W ...
Page 84
... This register control the bus tenure of the GMCH on AGP/PCI the same way Device 0 MLT controls the access to the PCI_A bus. Bit 7:3 Secondary MLT Counter Value (MLT). Programmable, default = 0 (SMLT disabled) 2:0 Reserved. 84 19h 00h R/W 8 bits Description 1Ah 00h R/W 8 bits Description 1Bh 00h RO, R/W 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 85
... Bit I/O Address Limit (IOLIMIT). This field corresponds to A[15:12] of the I/O address limit of Device 1. 7:4 Devices between this upper limit and IOBASE1 will be passed to AGP/PCI_B. 3:0 Reserved. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 1Ch F0h RO, R/W 8 bits Description 1Dh ...
Page 86
... Fast Back-to-Back (FB2B)—RO. Hardwired to 1. GMCH target, supports fast back-to-back 7 transactions on PCI_B/AGP. 6 Reserved. 66/60 MHz Capability (CAP66)—RO. Hardwired to 1. Indicates that the AGP/PCI_B bus is capable MHz operation. 4:0 Reserved. 86 1Eh 02A0h RO, R/WC 16 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 87
... Bit Memory Address Base (MBASE). This field corresponds to A[31:20] of the lower limit of the 15:4 memory range that will be passed by the Device 1 bridge to AGP/PCI_B. 3:0 Reserved. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 20–21h FFF0h R/W 16 bits Description Register Description ...
Page 88
... Bit Memory Address Limit (MLIMIT). Corresponds to A[31:20] of the memory address that corresponds 15:4 to the upper limit of the range of memory accesses that will be passed by the Device 1 bridge to AGP/ PCI_B. 3:0 Reserved. 88 22–23h 0000h RO, R/W 16 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 89
... Bit Prefetchable Memory Address Limit (PMLIMIT). This field corresponds to A[31:20] of the upper 15:4 limit of the address range passed by bridge Device 1 across AGP/PCI_B. 3:0 Reserved. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 24–25h FFF0h R/W 16 bits Description 26–27h ...
Page 90
... Other types of error conditions can still be signaled via SERR messaging independent of this bit’s state Enable. Address and data parity errors detected on PCI_B are reported via the HI SERR messaging mechanism, if further enabled by SERRE1. 90 3Eh 00h RO, R/W 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 91
... PCI_B Enable. The GMCH generates an SERR message over the hub interface upon receiving a target abort on PCI_B. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Description All References to MDA and VGA space are routed to hub interface. Illegal combination All VGA references are routed to this bus. MDA references are routed to the hub interface ...
Page 92
... Video Bids ROM Base Address Capabilities Pointer Intel Reserved Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Intel Reserved Power Management Capabilities ID Power Management Capabilities Power Management Control Intel Reserved ® Intel 82845G/82845GL/82845GV GMCH Datasheet Table 3-5 provides the register Default Access Value 8086h RO ...
Page 93
... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel = 8086. 3.5.3.2 DID2—Device Identification Register (Device 2) Address Offset: Default Value: ...
Page 94
... Memory Access Enable (MAE)—R/W. This bit controls the IGD’s response to memory space accesses Disable (default Enable. I/O Access Enable (IOAE)—R/W. This bit controls the IGD’s response to I/O space accesses Disable (default Enable. 94 04h−05h 0000h RO, R/W 16 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 95
... Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the IGD. 82845G and 82845GL GMCH 01h = A1 Stepping 7:0 03h = B1 Stepping 82845GV GMCH 01h = A1 Stepping ® Intel 82845G/82845GL/82845GV GMCH Datasheet 06h−07h 0090h RO, R/WC 16 bits Description 08h See table below ...
Page 96
... The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit 7:0 Master Latency Timer Count Value. Hardwired to zeros. 96 09h−0Bh 030000h RO 24 bits Description 0Ch 00h RO 8 bits Description 0Dh 00h RO 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 97
... Address Mask—RO. Hardwired to zeros to indicate (at least) a 32-MB address range. 3 Prefetchable Memory—RO. Hardwired enable prefetching. 2:1 Memory Type—RO. Hardwired indicate 32-bit address. 0 Memory/IO Space—RO. Hardwired indicate memory space. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 0Eh 00h RO 8 bits Description 10−13h ...
Page 98
... BIOS during boot-up. Once written, this register becomes read only. This register can only be cleared by a Reset. 98 14– 17h 00000000h R/ bits Description 2C– 2Dh 0000h R/WO 16 bits Description 2E– 2Fh 0000h R/WO 16 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 99
... This register is needed for Plug N Play software. Settings of this register field has no effect on GMCH operation as there is no hardware functionality associated with this register, other than the hardware implementation of the R/W register itself. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 30–33h 00000000h ...
Page 100
... CAP_ID. SIG defines this ID is 01h for power management. 100 3Dh 01h RO 8 bits Description 3Eh 00h RO 8 bits Description 3Fh 00h RO 8 bits Description D0h−D1h 0001h RO 16 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 101
... D0 (Default) 1 Not Supported– Writes will be blocked and will return the previous value Not Supported– Writes will be blocked and will return the previous value ® Intel 82845G/82845GL/82845GV GMCH Datasheet D2h−D3h 0021h RO 16 bits Description D4h− ...
Page 102
... Register Description 3.5.4 Device 6 Registers Device 6 registers are Intel Reserved, except for the following two registers. 3.5.4.1 DWTC—DRAM Write Throttling Control Register (Device 6) Address Offset Default Value Access Size: Bits 63:41 Intel Reserved. Global Write Hexword Threshold (GWHT). The thirteen-bit value held in this field is multiplied by ...
Page 103
... Address Offset Default Value Access Size: Bits 63:41 Intel Reserved. Global Read Hexword Threshold (GRHT). The thirteen-bit value held in this field is multiplied by 15 40: arrive at the number of hexwords that must be read within the Global DRAM Read Sampling Window in order to cause the throttling mechanism to be invoked. ...
Page 104
... Register Description 104 This page is intentionally left blank. ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 105
... Table 4-1). Table 4-1. DINV Signals vs. Data Bytes DINV[3:0]# DINV_0# DINV_1# DINV_2# DINV_3# ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description [3:0]# indicate if _ Data Bits HD_[15:0]# HD_[31:16]# HD_[47:32]# HD_[63:48]# 4 ...
Page 106
... Once posted, the memory write from AGP or the hub interface, to address 0FEEx_xxxxh, is decoded as a cycle that needs to be propagated by the GMCH to the system bus as an Interrupt Message Transaction. 106 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 107
... SDRAM technology. The eight chip select lines support up to four rows of double-sided SDRAM DIMMs. For write operations of less than a QWord, the GMCH performs a byte-wise write. The GMCH does not support ECC DIMMs, registered DIMMs, mixed-mode (uneven) DS DIMMs, or PC100 DIMMs. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description 107 ...
Page 108
... SDR DIMM configurations. 128 Mbit X16 X8 X16 X8 SS/DS SS/DS SS/DS SS/ 128 256 256 MB 128 MB 512 MB ® Intel 82845G/82845GL/82845GV GMCH Datasheet 256 Mbit 512 Mbit X16 X8 X16 SS/DS SS/DS SS/DS 128 MB / 512 MB / 256 MB/ NA 1024 MB NA 256 Mbit 512 Mbit X16 ...
Page 109
... GMCH memory interface. SMBus Configuration and Access of the Serial Presence Detect Ports For more details, refer to the Intel Memory Register Programming This section provides an overview of how the required information for programming the SDRAM registers is obtained from the Serial Presence Detect ports on the DIMMs ...
Page 110
... One measure of performance is the total flight time to complete a cache line request. A true discussion of performance involves the entire chipset, not just the system memory controller. 110 [26 [26 [26 [27 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 111
... If the processor has established a lock to another resource other than AGP, the GMCH will accept incoming FRAME# cycles based on the other retry/disconnect rules. Since snoops cannot be generated to the processor while a lock is outstanding, eventually the GMCH’s PCI interface backs up. ® Intel 82845G/82845GL/82845GV GMCH Datasheet 4.5. Functional Description 111 ...
Page 112
... N/A 1110 N/A 1111 N/A 4-6. The GMCH supports both normal and high priority read and write ® Intel 82845G/82845GL/82845GV GMCH Datasheet GMCH Host Bridge Response As AGP Target Low Priority Read Complete with random data High Priority Read Complete with random data ...
Page 113
... Traffic between AGP and hub interface is limited to hub interface-to-AGP memory writes. • LOCK# signal is not present. Neither inbound nor outbound locks are supported. • SERR#/PERR# signals are not present. • 16 clock Subsequent Data Latency timer (instead of 8). ® Intel 82845G/82845GL/82845GV GMCH Datasheet 3 Functional Description 113 ...
Page 114
... FW transactions follow a combination for PCI and AGP bus protocols for data movement. 4.3.1.8 AGP 1.5 V Connector GMCH’s AGP buffers only support 1.5 V operation. Therefore, 845G chipsets only support 1.5 V AGP connectors. 114 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 115
... Subsequent memory read transaction hitting the cache line buffer return data from the buffer. ® Intel 82845G/82845GL/82845GV GMCH Datasheet GC/BE[3:0]# Encoding Cycle Destination ...
Page 116
... Length = 8 Bytes with All BEs Asserted Length = 16 Bytes Length = 32 Bytes Code Only Length < 8 Bytes without All BEs Asserted Length = 16 Bytes Length = 32 Bytes All Combinations All Combinations ® Intel 82845G/82845GL/82845GV GMCH Datasheet Table 4-8 GMCH Host Bridge Corresponding GC/BE[3:0]# PCI_B Command Encoding None ...
Page 117
... GMCH Retry/Disconnect Conditions The GMCH generates retry/disconnect according to the Accelerated Graphics Port Interface Specification, Revision 2.0 rules when being accessed as a target from the AGP interface (using PCI semantics). ® Intel 82845G/82845GL/82845GV GMCH Datasheet Other Encoded Information Address ≥ Functional Description ...
Page 118
... AGP request is generated. • If AGP Inbound buffers become full during the burst, the GMCH disconnects within 8 clocks if there is an AGP non-snoopable request or host bridge-to-AGP request present. An AGP-DRAM burst is disconnected after crossing the 2-KB address boundary. 118 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 119
... High-bandwidth access to data is provided through the system memory port. The GMCH can access graphics data located in system memory at 1.0 GB/s (using SDR, PC133 memory), 1.6 GB/s (using DDR200 memory), and 2.1 GB/s (using DDR266). The GMCH uses Intel’s Direct Memory Execution model to fetch textures from system memory. The GMCH includes a cache controller to avoid frequent memory fetches of recently used texture data ...
Page 120
... A scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger region than the hardware renders to. The scissor rectangle needs to be pixel accurate, and independent of line and point width. The GMCH will support a single scissor box rectangle, which can be enabled or disabled. 120 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 121
... Texture Engine The GMCH allows an image, pattern, or video to be placed on the surface polygon. The texture processor performs texture color or chromakey matching, texture filtering (anisotropic, trilinear and bilinear interpolation), and YUV-to-RGB conversions. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description 121 ...
Page 122
... The way a texture is combined with other object attributes is also definable. The GMCH supports Levels-of-Detail (LODs) ranging in size from 2048x2048 to 1x1 texels. (A texel is defined as a texture map element). Textures need not be square. Included in the texture processor is a texture cache that provides efficient MIP-mapping. 122 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 123
... Texel values are then read from the intersection point on the appropriate face and filtered accordingly. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description 123 ...
Page 124
... Input color, alpha, and fog components are converted from 8-bit components bit component by dithering. Dithering is performed on blended texture pixels. In 32-bit mode, dithering is not performed on the components. 124 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 125
... This also speeds up the display process over a single buffer. Additionally, triple back buffering is also supported. The instruction set of the GMCH provides a variety of controls for the buffers (e.g., initializing, flip, clear, etc.). ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description 125 ...
Page 126
... The Stretch BLT engine is used to move source data to a destination that need not be the same size, with source transparency. Performing these common tasks in hardware reduces processor load and, thus, improves performance. 126 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 127
... GMCH VGA Registers The 2D registers are a combination of registers defined by IBM when the Video Graphics Array (VGA) was first introduced and others that Intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard ...
Page 128
... Cursor Plane The cursor plane is one of the simplest display planes. With a few exceptions, it has a fixed size of 64x64 and a fixed Z-order (top). In legacy modes, the cursor can cause the display data below inverted. 128 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 129
... The compromise is to provide low cost but effective solutions and enable both hardware and software based external solutions. Software-based solutions are enabled through a high bandwidth transfer to system memory and back. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description 129 ...
Page 130
... MHz –350 MHz. Accuracy for VESA timing modes is required to be within ± 0.5%. The DPLL can take a reference frequency from the external reference input (DREFCLK) or the TV clock input (DVOBC_CLKINT). 4.4.4 Ports For more information on ports, refer to 130 Section 4.5. ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 131
... External Device Connector Special Functions NOTE: 1. Single signal software selectable between display enable and Blank#. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Analog Digital Port B ® RGB DAC Intel DVO 2.0 Yes Enable/Polarity Yes Enable/Polarity (1) No Yes No Yes No Yes No Programmable and typically 1.33:1 or 1.78:1 ...
Page 132
... Analog Copy Protection No Sync on Green No Voltage LVTTL Enable/Disable Port control Polarity adjust VGA or port control Composite Sync Support No Special Flat Panel Sync No Stereo Sync No 3.3 V – may need to be externally Voltage buffered Control Through GPIO interface ® Intel 82845G/82845GL/82845GV GMCH Datasheet Support ...
Page 133
... The GMCH provides unscaled mode where the display is centered on the panel. The GMCH supports scaling in the LVDS transmitter through the DVOB (or DVOC)_STL pin, multiplexed with DVOB (or DVOC)_FLD. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description 133 ...
Page 134
... Macrovision TV encoder before playback continues. Simple attempts to disable the Macrovision operation must be detected. Connectors Target TV connector support includes the CVBS, S-Video, Component, and SCART connectors. The external TV encoder in use determines the method of support. 134 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 135
... use. The GMCH does not support two synchronous digital displays. The GMCH cannot drive multiple displays concurrently (different data or timings). In addition, the GMCH cannot operate in parallel with an external AGP device. The GMCH can, however, work in conjunction with a PCI graphics adapter. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description 135 ...
Page 136
... GMCH graphics functions. The GMCH graphics functions enter this state out of power-on- reset. • D3 (Inactive): The D3 power state is the lowest power mode. Displays are off, and the registers and memory need not be maintained. HSYNC and VSYNC are not pulsed in this state. 136 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 137
... The graphics core and display interfaces are asynchronous to the rest of the GMCH. The Graphics core runs at 200 MHz. The display PLL uses the Non-Spread Spectrum 48 MHz input to generate a frequency range of 12 MHz–350 MHz. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Functional Description 137 ...
Page 138
... Functional Description ® Figure 4-2. Intel 845G Chipset-Based System Clocking Diagram Low Voltage Differential Clocks Low Voltage Differential Clocks 100/133 MHz CK- 408 Main PLL 400 MHz 100/ 133 MHz ITP 138 Processor 100/133 MHz Host PLL GMCH DPLL Core 24 - 350 PLL ...
Page 139
... AGP, High BIOS, and APIC memory space can be allocated. Figure 5-1 shows the system memory address map in a simplified form. additional details on mapping specific memory regions as defined and supported by the GMCH. ® Intel 82845G/82845GL/82845GV GMCH Datasheet System Address 5 Figure 5-2 provides ...
Page 140
... Non-overlapping Windows System Memory Space Max TOM AGP Window PCI 2 GB Range 16 MB Optional ISA Hole 640 ® Intel 82845G/82845GL/82845GV GMCH Datasheet AGP Graphics Aperture Graphics Aperture 0FFFFFh 1 MB Upper BIOS Area (64 KB) 0F0000h 960 KB 0EFFFFh Lower BIOS Area (64 KB 0E0000h ...
Page 141
... GMCH always positively decodes internally mapped devices (IGD and AGP/PCI_B). Subsequent decoding of regions mapped to AGP/PCI_B or the hub interface depends on the Legacy VGA configurations bits (VGA Enable and MDAP). This region is also the default for SMM space. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Attributes fixed - always mapped to main 0 to 640K – ...
Page 142
... This area is a single, 64-KB segment. This segment can be assigned read and write attributes default (after reset) read/write disabled and cycles are forwarded to the hub interface. By manipulating the read/write attributes, the GMCH can “shadow” BIOS into the main SDRAM. When disabled, this segment is not remapped. 142 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 143
... TOM) are created for SMM-mode and legacy VGA graphics compatibility. For VGA graphics compatibility, pre-allocated memory is only required in non-local memory configurations. Note the responsibility of BIOS to properly initialize these regions. ® Intel 82845G/82845GL/82845GV GMCH Datasheet System Address 143 ...
Page 144
... SDRAM minus the value in the TSEG register. 144 Attributes R/W Available System Memory 62.5 MB Pre-allocated Graphics VGA memory. R (or 512 MB) when IGD is enabled. SMM Mode Only - processor TSEG Address Range reads SMM Mode Only - processor TSEG Pre-allocated Memory reads ® Intel 82845G/82845GL/82845GV GMCH Datasheet Comments ...
Page 145
... High BIOS after reset. This region is mapped to the hub interface so that the upper subset of this region aliases to 16 MB–256 KB range. The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region that the full 2 MB must be considered. ® Intel 82845G/82845GL/82845GV GMCH Datasheet System Address 145 ...
Page 146
... PCI devices. The PCICMD1 register can override the routing of memory accesses to AGP. In other words, the Memory Access Enable bit must be set in the Device 1 PCICMD1 register to enable the memory base/limit and prefetchable base/limit windows. 146 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 147
... GMCH Package Thermal Resistance Parameter Ψ ( ° C/Watt)** jt Θ ( ° C/Watt)** ja NOTE: Refer to the Intel Memory Controller Hub (GMCH) Thermal and Mechanical Design Guidelines for more information. ® Intel 82845G/82845GL/82845GV GMCH Datasheet Parameter Die Temperature under Bias Storage Temperature 1.5 V Supply Voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS 2 ...
Page 148
... VCCSM(SDR) I 3.3 V Standby Supply Current SUS_3.3 NOTES: ® 1. See Intel 845G/845GL/845GV Chipset: Intel Hub (GMCH) Thermal and Mechanical Design Guidelines for more information. 2. These current levels may happen simultaneously and can be summed into one supply. 6.4 Signal Groups The signal description includes the type of buffer used for the particular signal (see ...
Page 149
... DVO Signal Groups (w) DVOx Input (x) DVOx Output Reset and Miscellaneous Signal Groups (y) CMOS I/O ® Intel 82845G/82845GL/82845GV GMCH Datasheet Signals HI_[10:0], HISTBS, HISTBF HI_SWING, HI_VREF, HI_RCOMP ADS#, BNR#, DBSY#, DINV_[3:0]#, DRDY#, HA_[31:3]#, HADSTB_[1:0] #, HD_[63:0]#,HDSTBP_[3:0]#, HDSTBN_[3:0]#, HIT#, HITM#, HREQ_[4:0]# HLOCK# BPRI#, BREQ0#, CPURST#, DEFER#, HTRDY#, RS_[2:0]# ...
Page 150
... VCCAGP – 2% 0.343 0.686 2/3 x VTT – 2% 1/3 x VTT – 2% 2/3 x VTT – 2% 0.5 VCCSM (DDR) – 2% 0.5 VCCSM (SDR) – 2% ® Intel 82845G/82845GL/82845GV GMCH Datasheet Nom Max Unit 1.5 1.575 V 1.5 1.575 V 1.5 1.575 V 1.5 1.575 ...
Page 151
... Table 6-6. DC Characteristics (Sheet Signal Symbol Parameter Group ® 1.5 V AGP and Intel DVO Interface: Functional Operating Range (VCC=1.5 V ± 5%) V (a,b,w) AGP/DVO Input Low Voltage IL_AGP V (a,b,w) AGP/DVO Input High Voltage IH_AGP V (a,c,x) AGP/DVO Output Low Voltage OL_AGP V (a,c,x) AGP/DVO Output High Voltage ...
Page 152
... Note 5 Note 5 measured by the oscilloscope. IH –0.71); V Minimum = 0.550+0.5(V IH(Ave) Cross(Rel) ® Intel 82845G/82845GL/82845GV GMCH Datasheet Unit Notes max OL_SDR mA @V max OH_SDR 0<Vin< µ A VCCSM(SDR MHz ...
Page 153
... Defined for a double 75 Ω termination 5. Set by external reference resistor value 6. INL and DNL measured & calculated according to VESA Video Signal Standards 7. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage) ® Intel 82845G/82845GL/82845GV GMCH Datasheet Vcross(rel) Max 550 500 ...
Page 154
... V 0.5 % ® Intel 82845G/82845GL/82845GV GMCH Datasheet Notes 1% tolerance, 1/16 W Note 1, 1% tolerance, 1/16 W Note 2, 1% tolerance, 1/16 W (applies to differential routing) Note 3, @ 100 MHz, (each RED, GREEN, BLUE output) Note 3, two capacitors per RED, GREEN, BLUE output Notes Notes 1, 2, (10– ...
Page 155
... Refer to Section 2.5.1 Note Connect. Note: RSVD = These pins should not be connected and should be allowed to float. ® Intel 82845G/82845GL/82845GV GMCH Datasheet show the 82845G GMCH footprint with the ball names listed for each Table 7-2 for the SDR-to-DDR signal mapping. for the DVO-to-AGP signal mapping. ...
Page 156
... Ballout and Package Information ® Figure 7-1. Intel 82845G GMCH Ballout Footprint (Top View – Left Side VSS VCCSM AT NC VSS SDQ_55 SDQS_6 SDQ_53 SDQ_49 AR VSS SDQ_50 VSS SDM_6 VSS SDQ_48 SCMD AP SDQ_60 SDQ_51 SDQ_54 SDQ_52 CLK_5 SCMD AN VSS SDQ_56 VSS ...
Page 157
... Figure 7-2. Intel 82845G GMCH Ballout Footprint (Top View – Right Side VCCSM VSS VCCSM SDQ_26 SDQS_3 SDQ_29 SDQ_24 SDQ_19 SDQ_18 SDM_3 VSS SDQ_28 VSS SDQ_22 VSS SDQ_30 SMAA_7 SDQ_25 VCCSM SDQ_23 SCKE_0 SMAA_8 SMAA_12 SCKE_1 VCCSM VSS VCCSM SMAA_5 ...
Page 158
... HD_55# C25 VSS C26 DINV_3# C27 VSS C28 HD_47# C29 VSS C30 HDSTB_N2# ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-1. Intel 82845G GMCH Ballout by Ball Number Ball # Signal Name C31 VSS C32 HD_41# C33 VSS C34 HD_37# C35 DINV_1# C36 ...
Page 159
... F32 VSS F34 HD_21# F35 HD_24# F36 HD_20# G1 VCCAGP ® Intel 82845G/82845GL/82845GV GMCH Datasheet Ballout and Package Information ® Table 7-1. Intel 82845G Table 7-1. Intel GMCH Ballout by Ball GMCH Ballout by Ball Number Number Ball # Signal Name G2 GAD_24 J2 G3 VSS J3 G4 ...
Page 160
... GAD_6 U3 VSS U4 GAD_5 U5 GAD_4 U7 GADSTB_0# U9 VSS U17 VCC U18 VSS ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-1. Intel 82845G GMCH Ballout by Ball Number Ball # Signal Name U19 VCC U20 VSS U21 VCC U29 VSS U31 DBSY# U33 BREQ0# U34 RS_1# ...
Page 161
... AB4 VSS AB6 VSS AB8 HI_1 AB10 VCCAGP ® Intel 82845G/82845GL/82845GV GMCH Datasheet Ballout and Package Information ® Table 7-1. Intel 82845G Table 7-1. Intel GMCH Ballout by Ball GMCH Ballout by Ball Number Number Ball # Signal Name AB28 VSS AE35 AB30 HA_5# ...
Page 162
... VCCSM AM16 VSS AM18 VCCSM AM20 VSS AM22 VCCSM AM24 VSS AM26 VCCSM ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-1. Intel 82845G GMCH Ballout by Ball Number Ball # Signal Name AM28 VSS AM30 VCCSM AM32 VSS AM34 SCMDCLK_2 AM35 SDQ_61 AM36 ...
Page 163
... AR19 VSS AR20 SDQ_31 AR21 VSS AR22 SDQ_32 ® Intel 82845G/82845GL/82845GV GMCH Datasheet Ballout and Package Information ® Table 7-1. Intel 82845G Table 7-1. Intel GMCH Ballout by Ball GMCH Ballout by Ball Number Number Ball # Signal Name AR23 VSS AT29 AR24 SDQS_4 ...
Page 164
... GST_0 C4 J2 GST_1 B4 M3 GST_2 B3 L5 GSTOP GTRDY GWBF# G5 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-2. Intel 82845G GMCH Ballout by Signal Name Signal Name Ball # HA_3# W31 HA_4# AA33 HA_5# AB30 HA_6# V34 HA_7# Y36 HA_8# AC33 HA_9# Y35 HA_10# ...
Page 165
... HD_38# HD_39# HD_40# HD_41# HD_42# HD_43# HD_44# HD_45# HD_46# HD_47# HD_48# HD_49# HD_50# ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-2. Intel 82845G GMCH Ballout by Signal Name Ball # Signal Name Ball # J36 HD_51# B26 K34 HD_52# G27 K36 HD_53# H26 M30 ...
Page 166
... AP35 AR6 SDQ_52 AP32 AT9 SDQ_53 AT33 AR10 SDQ_54 AP34 AT6 SDQ_55 AT35 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-2. Intel 82845G GMCH Ballout by Signal Name Signal Name Ball # SDQ_56 AN36 SDQ_57 AM36 SDQ_58 AK36 SDQ_59 AJ36 SDQ_60 AP36 SDQ_61 ...
Page 167
... VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA_DAC VCCA_DAC ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-2. Intel 82845G GMCH Ballout by Signal Name Ball # Signal Name Ball # B9 VCCA_DPLL A13 B10 VCCA_FSB A17 B11 VCCA_HI AD10 B12 VCCA_SM ...
Page 168
... E21 VSS N29 E35 VSS N35 E37 VSS N37 F6 VSS P28 F8 VSS P32 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-2. Intel 82845G GMCH Ballout by Signal Name Signal Name Ball # VSS R3 VSS R29 VSS R35 VSS T6 VSS T10 VSS T32 VSS ...
Page 169
... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 7-2. Intel 82845G GMCH Ballout by Signal Name Ball # Signal Name Ball # AC29 VSS AM20 AC35 VSS AM24 AD32 VSS AM28 AE1 ...
Page 170
... Ballout and Package Information 7.2 Package Information The GMCH 37 37.5 mm FC-BGA package with 1 mm ball pitch. show the package dimensions. ® Figure 7-3. Intel 82845G GMCH Package Dimensions (Top and Side Views) 18.75 17.9250 37.50 ±0.05 Detail A 0.203 C ϕ 0.6500 ±0.05 ϕ ...
Page 171
... Figure 7-4. Intel 82845G GMCH Package Dimensions (Bottom View) 0.7500 0.7500 1.0000 Detail B 0.57 ±0.1 Units = Millimeters ® Intel 82845G/82845GL/82845GV GMCH Datasheet Bottom View 1.0000 Detail B Pin A1 0.7 ±0.05 0.7 ±0.05 0.57 ±0.1 0.7 ±0.05 Ballout and Package Information Detail A ...
Page 172
... Ballout and Package Information 172 This page is intentionally left blank. ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 173
... All XOR chains can be run in parallel except chains with AGP strobes. Thus, chain 0 and chain 1 cannot be run in parallel; similarly chain 2 and chain 3. Note: The Channel A and Channel B output pins for each Chain show the same output. ® Intel 82845G/82845GL/82845GV GMCH Datasheet DDR Output Pin Channel A ...
Page 174
... GSBA_0 W4 GST_0 W5 GST_2 V2 HSYNC U2 DDCA_CLK V4 DDCA_DATA V3 Output Pins U4 SMAA_1 U5 SMAA_8 ® Intel 82845G/82845GL/82845GV GMCH Datasheet XOR Chain 2 (25 inputs) Output pins: SMAA_2, SMAA_9 Ball # Signal Name V8 MEM_SEL Y2 D5 RSVD AA2 G7 RSVD AA3 H8 PSB_SEL Y3 E2 RSVD Y4 F3 GAD_18 K2 F2 GAD_20 M3 D2 GAD_16 P8 ...
Page 175
... GDEVSEL# GTRDY# GWBF# GC/BE_2# GC/BE_3# GSBSTB Output Pins SMAA_0 SMAA_7 175 XOR Chain 1 (18 inputs) Output pins: SMAA_1, SMAA_8 Ball # Signal Name AL25 AP17 ® Intel 82845G/82845GL/82845GV GMCH Datasheet XOR Chain 2 (25 inputs) Output pins: SMAA_2, SMAA_9 Ball # Signal Name Ball # ...
Page 176
... B30 HDSTBP_0# L31 D29 HDSTBN_0# N31 B34 DINVB_0 N33 E29 HD_1# R33 C30 HD_7# P35 ® Intel 82845G/82845GL/82845GV GMCH Datasheet XOR Chain 5 (46 inputs) Output pins: SMAA_5, SMAA_12 Signal Name Ball # SDQ_59 AJ36 SDQ_62 AK35 SDQ_58 AK36 SDQ_63 AK34 SDM_7 AL34 ...
Page 177
... Output pins: SMAA_3, SMAA_10 Signal Name CPURST# HD_39# HD_33# HD_37# HD_36# HD_41# HD_35# HD_32# HD_40# Output Pins SMAA_3 SMAA_10 ® Intel 82845G/82845GL/82845GV GMCH Datasheet XOR Chain 4 (51 inputs) Output pins: SMAA_4, SMAA_11 Ball # Signal Name Ball # D22 HD_4# R31 D31 HD_0# T30 D30 ...
Page 178
... AT4 SDQ_3 AP5 SDQ_5 AP3 SDQ_6 AR4 SDM_0 AP4 SDQ_4 AN2 SDQ_0 AN4 SDQS_0 AR2 ® Intel 82845G/82845GL/82845GV GMCH Datasheet XOR Chain 8 (33 inputs) Output pins: SBA_0, SBA_1 Signal Name Ball # HA_7# Y36 HA_6# V34 HREQ_2# W33 HA_9# Y35 HA_13# Y34 ...
Page 179
... Table 8-4. XOR Chains 6, 7, and 8 (Sheet XOR Chain 6 (20 inputs) Output pins: SMAA_6, SWE# Signal Name ® Intel 82845G/82845GL/82845GV GMCH Datasheet XOR Chain 7 (40 inputs) Output pins: SRAS#, SCAS# Ball # Signal Name Ball # SDQ_2 AT3 SDQ_1 AP2 Output Pins SRAS# ...
Page 180
... VCCA_FSB AD10, AD14 HCLKN AE7 HCLKP AD3 HD_VREF_0 AC2 HCC_VREF AD2 HA_VREF AB2 HY_RCOMP W2 PWROK L2 DREFCLK ® Intel 82845G/82845GL/82845GV GMCH Datasheet Ball # Y30 AJ31 AJ34 AD16, AF10 B16 B15, C14 A15, B14 D27 B28 H28 H24 A17 J31 K30 H30 P30 ...
Page 181
... The information in this chapter applies to both the 82845GL and 82845GV components, unless otherwise noted. Also, unless otherwise noted in this chapter, GMCH applies to both the 82845GL and 82845GV components. ® Figure 9-1. Intel 845GL/845GV Chipset System Block Diagram 2 Intel Ports 4 IDE Devices ...
Page 182
... DVO select bit in the GMCHCFG register will be set to DVO mode. Motherboards that use this interface in a DVO down scenario should have a pull-down resistor on ADD_DETECT. ® Section 2.5.1, Intel DVO Signals Name to AGP Signal Name Pin the PSBSEL signal description is replaced by the following: Description PSB Frequency Select: The PSBSEL is tied to the external BSEL resistor-divider circuitry ...
Page 183
... The Device 2 registers are the same for the 82845G and 82845GL/82845GV. 9.4.1 DRAM Controller/Host-Hub Interface Device Registers (Device 0) 9.4.1.1 Device 0 Registers Not in 82845GL/82845GV The following registers are not in the 82845GL82845GV and the address locations are Intel Reserved. — APBASE Aperture Base Configuration Register (Device 0) Address Offset: Size: — ...
Page 184
... Device 1 flow through to the hub interface. Also, the Next_Pointer field in the CAPREG register (Device 0, Offset E4h 00h. This enables internal graphics 3 capability Enable. Internal Graphics is enabled (default) 184 B8–BBh 32 bits BC–BFh 8 bits BDh 8 bits Chapter 3. 52h 0000_0000b RO 8 bits Description ® Intel 82845G/82845GL/82845GV GMCH Datasheet ...
Page 185
... Next Pointer field in CAPREG will be hardwired to zeros. ERRSTS—Error Status Register (Device 0) Address Offset Default Value Access Size: Bits 4:0 Intel Reserved ERRCMD—Error Command Register (Device 0) Address Offset Default Value Access Size: Bits 4:0 Intel Reserved ® ...
Page 186
... Device 1 does not exist on the 82845GL/82845GV components. The Device 1 registers described in Chapter 3. are not in the 82845GL/82845GV. For the 82845GL/82845GV, these register address locations are Intel Reserved. 9.5 Synchronous Display Differences The synchronous display is different between the 82845G and 82845GL\82845GV. For the ...
Page 187
... ADDID2 D3 R7 ADDID3 D2 T8 ADDID4 E4 P3 ADDID5 E2 P8 ADDID6 F3 K4 ADDID7 F2 ® Intel 82845GL/82845GV GMCH ® Table 9-1. Intel 82845GL/ 82845GV Ballout by Signal Name Signal Name Ball# MDDC_DATA P2 MDVI_CLK N5 HA_3# W31 HA_4# AA33 HA_5# AB30 HA_6# V34 HA_7# Y36 HA_8# AC33 ...
Page 188
... HDSTB_N3# C36 HDSTB_P0# D33 HDSTB_P1# D30 HDSTB_P2# D29 HDSTB_P3# E31 HDVREF_0 D32 HDVREF_1 ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 9-1. Intel 82845GL/ 82845GV Ballout by Signal Name Ball# Signal Name Ball# C34 HDVREF_2 D27 B34 HI_0 AA7 D31 HI_1 AB8 G29 ...
Page 189
... AP5 AA5 SDQ_4 AN2 AB3 SDQ_5 AP3 AN27 SDQ_6 AR4 AP27 SDQ_7 AT4 ® Intel 82845GL/82845GV GMCH ® Table 9-1. Intel 82845GL/ 82845GV Ballout by Signal Name Signal Name Ball# SDQ_8 AT5 SDQ_9 AR6 SDQ_10 AT9 SDQ_11 AR10 SDQ_12 AT6 SDQ_13 AP6 ...
Page 190
... VCC AK20 VCC AL19 VCC AL17 VCC AP19 VCC AP17 VCC AN17 VCC ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 9-1. Intel 82845GL/ 82845GV Ballout by Signal Name Ball# Signal Name Ball# AK16 VCC H14 AK26 VCC J11 AL15 VCC J13 AN15 ...
Page 191
... VCCSM AU25 AJ5 VCCSM AU29 AJ7 VCCSM AU33 AJ9 VSS A5 AJ11 VSS A21 ® Intel 82845GL/82845GV GMCH ® Table 9-1. Intel 82845GL/ 82845GV Ballout by Signal Name Signal Name Ball# VSS A23 VSS A25 VSS A27 VSS A29 VSS A33 VSS A35 ...
Page 192
... VSS K24 VSS K28 VSS K32 VSS L3 VSS L29 VSS L35 VSS M6 VSS ® Intel 82845G/82845GL/82845GV GMCH Datasheet ® Table 9-1. Intel 82845GL/ 82845GV Ballout by Signal Name Ball# Signal Name Ball# M10 VSS Y18 M32 VSS Y20 N1 VSS Y21 N3 VSS Y32 ...
Page 193
... AC37 AR1 VTTFSB B18 AR3 VTTFSB B19 AR5 VTTFSB B20 AR7 VTTFSB C18 ® Intel 82845GL/82845GV GMCH ® Table 9-1. Intel 82845GL/ 82845GV Ballout by Signal Name Signal Name Ball# VTTFSB C19 VTTFSB C20 VTTFSB D18 VTTFSB D19 VTTFSB D20 VTTFSB E19 ...