RG82845G S L66F Intel, RG82845G S L66F Datasheet - Page 75

• Manufacturer Part Number: RG82845G S L66F
• Manufacturer: Intel

Specifications of RG82845G S L66F

• Lead Free Status / RoHS Status: Not Compliant

3.5.1.34
Intel
®
82845G/82845GL/82845GV GMCH Datasheet
ERRCMD—Error Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register controls the GMCH responses to various system errors. Since the GMCH does not
have an SERR# signal, SERR messages are passed from the GMCH to the ICH over HI. When a
bit in this register is set, a SERR message will be generated on HI whenever the corresponding flag
is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for
Device 0 via the PCI Command register.
15:10
Bit
8:7
1:0
9
6
5
4
3
2
Intel Reserved.
SERR on Non-DRAM Lock (LCKERR).
1 = Disable.
1 = Enable. GMCH generates a HI SERR special cycle when a processor lock cycle is detected that
Intel Reserved.
SERR on Target Abort on HI Exception (TAHLA).
0 = Disable.
1 = Enable. GMCH generates an SERR special cycle over HI when an GMCH originated HI cycle is
SERR on Detecting HI Unimplemented Special Cycle (HIAUSCERR). SERR messaging for
Device 0 is globally enabled in the PCICMD register.
0 = Disable. GMCH does not generate an SERR message for this event.
1 = Enable. GMCH generates an SERR message over HI when an Unimplemented Special Cycle is
SERR on AGP Access Outside of Graphics Aperture (OOGF).
0 = Disable. Reporting of this condition is disabled.
1 = Enable. GMCH generates an SERR special cycle over HI when an AGP access occurs to an
SERR on Invalid AGP Access (IAAF).
0 = Disable. Invalid AGP Access condition is not reported.
1 = Enable. GMCH generates an SERR special cycle over HI when an AGP access occurs to an
SERR on Invalid Translation Table Entry (ITTEF).
0 = Disable. Reporting of this condition is disabled.
1 = Enable. GMCH generates an SERR special cycle over HI when an invalid translation table entry
Intel Reserved.
does not hit SDRAM.
completed with a Target Abort completion packet or special cycle.
received on the HI.
address outside of the graphics aperture.
address outside of the graphics aperture and either to the 640 KB –1 MB range or above the top
of memory. I
was returned in response to an AGP access to the graphics aperture.
CA–CBh
0000h
RO, R/W
16 bits
Description
Register Description
75