LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 84

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater
detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional
single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link
and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer
capability.
Vocabulary
The following terms are used in this document:
These terms may be considered synonymous:
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14,
1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is:
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration
SMSC DS – LPC47M14X
assert:
forward:
reverse:
Pword:
8 bits.
1
0
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
Registers.
Host to Peripheral communication.
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false"
state.
Peripheral to Host communication
A port word; equal in size to the width of the LPC interface. For this implementation, PWord
A high level.
A low level.
compress
Addr/RLE
nBusy
PD7
D7
0
0
MODE
intrValue
nAck
PD6
D6
0
0
Direction
PError
PD5
D5
0
Parallel Port Data FIFO
Parallel Port IRQ
ECP Data FIFO
nErrIntrEn dmaEn serviceIntr
ackIntEn
Test FIFO
Select
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PD4
Address or RLE field
D4
1
SelectI
nFault
PD3
D3
n
0
PD2
nInit
D2
0
0
Parallel Port DMA
autofd
PD1
D1
full
0
0
strobe
empty
PD0
D0
0
0
Rev. 03/19/2001
NOTE
2
1
1
2
2
2
is always