LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 5

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

7
8
9
10 TIMING DIAGRAMS........................................................................................................................................... 177
11 PACKAGE OUTLINE ......................................................................................................................................... 200
12 APPENDIX - TEST MODE.................................................................................................................................. 201
13 REFERENCE DOCUMENTS.............................................................................................................................. 204
14 LPC47M14X REVISIONS ................................................................................................................................... 205
Table 1 – Super I/O Block Addresses ........................................................................................................................20
Table 2 – Hub Descriptor to be Modified....................................................................................................................25
Table 3 – Status, Data and Control Registers ............................................................................................................27
Table 4 – Tape Select Bits .........................................................................................................................................30
Table 5 – Internal 2 Drive Decode - Normal ...............................................................................................................30
Table 6 – Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................31
Table 7 – Drive Type ID .............................................................................................................................................31
Table 8 – Precompensation Delays ...........................................................................................................................32
Table 9 – Data Rates .................................................................................................................................................33
Table 10 – DRVDEN Mapping ...................................................................................................................................33
Table 11 – Default Precompensation Delays .............................................................................................................33
Table 12 – FIFO Service Delay ..................................................................................................................................35
Table 13 – Status Register 0......................................................................................................................................37
Table 14 – Status Register 1......................................................................................................................................38
Table 15 – Status Register 2......................................................................................................................................38
Table 16 – Status Register 3......................................................................................................................................39
Table 17 – Description of Command Symbols ...........................................................................................................41
Table 18 – Instruction Set ..........................................................................................................................................43
Table 19 – Sector Sizes .............................................................................................................................................50
Table 20 – Effects of MT and N Bits...........................................................................................................................51
Table 21 – Skip Bit vs Read Data Command .............................................................................................................51
SMSC DS – LPC47M14X
6.14
6.15
6.16
6.17
6.18
6.19
9.1
9.2
12.1
6.13.8
6.13.9
6.13.10 Keyboard and Mouse PME Generation ................................................................................................ 109
6.14.1
6.14.2
6.14.3
6.14.4
6.14.5
6.14.6
6.14.7
6.15.1
6.16.1
6.17.1
6.17.2
6.18.1
6.18.2
6.19.1
6.19.2
RUNTIME REGISTERS ...................................................................................................................................... 125
CONFIGURATION.............................................................................................................................................. 152
OPERATIONAL DESCRIPTION ........................................................................................................................ 172
12.1.1
GENERAL PURPOSE I/O.......................................................................................................................... 110
SYSTEM MANAGEMENT INTERRUPT (SMI)........................................................................................... 115
PME SUPPORT ......................................................................................................................................... 116
FAN SPEED CONTROL AND MONITORING............................................................................................ 118
SECURITY FEATURE ............................................................................................................................... 122
GAME PORT LOGIC.................................................................................................................................. 122
M
DC E
B
OARD
AXIMUM
Default Reset Conditions ...................................................................................................................... 105
Latches On Keyboard and Mouse IRQs ............................................................................................... 108
GPIO Pins............................................................................................................................................. 110
Description............................................................................................................................................ 111
GPIO Control ........................................................................................................................................ 112
GPIO Operation .................................................................................................................................... 112
GPIO PME and SMI Functionality......................................................................................................... 113
Either Edge Triggered Interrupts........................................................................................................... 114
LED Functionality.................................................................................................................................. 115
SMI Registers ....................................................................................................................................... 115
‘Wake on Specific Key’ Option.............................................................................................................. 117
Fan Speed Control................................................................................................................................ 118
Fan Tachometer Inputs......................................................................................................................... 119
GPIO Device Disable Register Control ................................................................................................. 122
Device Disable Register ....................................................................................................................... 122
Power Control Register......................................................................................................................... 124
VREF Pin.............................................................................................................................................. 124
XNOR-Chain Test Mode....................................................................................................................... 201
LECTRICAL
T
EST
G
UARANTEED
M
ODE
C
HARACTERISTICS
....................................................................................................................................... 201
R
ATINGS
...................................................................................................................172
................................................................................................................172
TABLES
Page 5
Rev. 03/19/2001