LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 157

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

SMSC DS – LPC47M14X
Device ID -
Hard wired
Default = 0x5F
on VCC POR,
VTR POR,
SOFT RESET and
HARD RESET
Device Rev
Hard wired
= Current Revision
PowerControl
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and
HARD RESET
Power Mgmt
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
OSC
Default = 0x44, on
VCC POR,
VTR POR and
HARD RESET
REGISTER
ADDRESS
0x22 R/W
0x23 R/W
0x24 R/W
0x20 R
0x21 R
Chip Level, SMSC Defined
A
identification. Bits[7:0] = 0x5F when read.
A read only register which provides device revision
information. Bits[7:0] = current revision when read.
Bit[0] FDC Power
Bit[1] Reserved
Bit[2] Game Port Power
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power (Note 1)
Bit[6] Serial Port 3 Power
Bit[7] Reserved
0: Power Off or Disabled
1: Power On or Enabled
Bit[0]
Management” section.)
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6] Serial Port 3
Bit[7] Reserved (read as 0)
For each bit above (except Reserved)
= 0
= 1
Bit[0] Reserved
Bit [1] PLL Control
= 0
= 1
Bits[3:2] OSC
= 01
= 10
= 00
= 11
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0
= 1
Note: For normal operation, bit 6 should be set.
Bit[7] Reserved
read
FDC
Intelligent Pwr Mgmt off
Intelligent Pwr Mgmt on
Osc is on, BRG clock is on.
Same as above (01) case.
Osc is on, BRG Clock Enabled.
Osc is off, BRG clock is disabled.
12-Bit Address Qualification
16-Bit Address Qualification
PLL is on (backward Compatible)
PLL is off
Page 157
only
(see
register
DESCRIPTION
Note
which
in
the
provides
“FDC
device
Power
STATE
C
C
C
C
C
Rev. 03/19/2001