LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 131

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

SMSC DS – LPC47M14X
PME_EN3
Default = 0x00
on VTR POR
PME_EN4
Default = 0x00
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(hex)
0C
0D
PME Wake Status Register 3
This register is used to enable individual LPC47M14x
PME wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake
source is active (“1”), if the source asserts a wake event
so that the associated status bit is “1” and the PME_En
bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake
source is inactive (“0”), the PME Wake Status register
will indicate the state of the wake source but will not
assert the nIO_PME signal.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_EN (Enable bit for group SMI signal for
PME)
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP27
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
PME Wake Enable Register 4
This register is used to enable individual LPC47M14x
PME wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake
source is active (“1”), if the source asserts a wake event
so that the associated status bit is “1” and the PME_En
bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake
source is inactive (“0”), the PME Wake Status register
will indicate the state of the wake source but will not
assert the nIO_PME signal.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP43
Bit[6] GP60
Bit[7] GP61
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Page 131
DESCRIPTION
Rev. 03/19/2001