LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 147

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

SMSC DS – LPC47M14X
GP5
Default = 0x00
on VTR POR
Bit 3 is reset on VCC
POR,
and VTR POR
GP6
Default = 0x00
N/A
N/A
N/A
INT_GEN1
Default = 0xFF
on VCC POR and
HARD RESET
INT_GEN2
Default = 0xFF
on VCC POR and
HARD RESET
on VTR POR
NAME
Hard
Reset
REG OFFSET
(R/W)
(R/W)
(R/W)
(R/W)
(hex)
(R)
(R)
(R)
4F
50
51
52
53
54
55
General Purpose I/0 Data Register 5
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
General Purpose I/0 Data Register 6
Bit[0] GP60
Bit[1] GP61
Bit[7:2] Reserved
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Interrupt Generating Register 1 (Note 8)
0=Corresponding Interrupt frame driven low in the SER
IRQ stream. This must be enabled through the INT_G
Configuration Register.
Bit[0] Reserved
Bit[1] nINT1
Bit[2] nINT2
Bit[3] nINT3
Bit[4] nINT4
Bit[5] nINT5
Bit[6] nINT6
Bit[7] nINT7
Note:
Interrupt Generating Register 2 (Note 8)
0=Corresponding Interrupt frame driven low in the SER
IRQ stream. This must be enabled through the INT_G
Configuration Register.
Bit[0] nINT8
Bit[1] nINT9
Bit[2] nINT10
Bit[3] nINT11
Bit[4] nINT12
Bit[5] nINT13
Bit[6] nINT14
Bit[7] nINT15
Note:
Page 147
To enable/disable this register see Logical
Device A (0xF1)
To enable/disable this register see Logical
Device A (0xF1)
DESCRIPTION
Rev. 03/19/2001