LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 21

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

6.3
The following sub-sections specify the implementation of the LPC bus.
6.3.1
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz
electrical signal characteristics.
Note: The CLKRUN# signal is not implemented in this part.
6.3.2
The following cycle types are supported by the LPC protocol.
The LPC47M14x ignores cycles that it does not support.
6.3.3
The data transfers are based on specific fields that are used in various combinations, depending on the cycle type.
These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the
LPC bus between the host and the LPC47M14x. See the “Low Pin Count (LPC) Interface Specification”, Revision
1.0, Section 4.2 for definition of these fields.
6.3.4
LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out
condition. This signal is to be used by the LPC47M14x to know when to monitor the bus for a cycle.
This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a
cycle, and that the LPC47M14x monitors the bus to determine whether the cycle is intended for it. The use of
LFRAME# allows the LPC47M14x to enter a lower power state internally. There is no need for the LPC47M14x to
monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks.
When the LPC47M14x samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the next
clock and monitor the bus for new cycle information.
The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification, Revision 1.0.
SMSC DS – LPC47M14X
PCI_RESET#
LFRAME#
nIO_PME
SER_IRQ
PCI_CLK
LAD[3:0]
LPCPD#
SIGNAL
LDRQ#
NAME
LPC INTERFACE
LPC Interface Signal Definition
LPC Cycles
Field Definitions
LFRAME# Usage
Output
TYPE
Input
Input
Input
Input
OD
I/O
I/O
CYCLE TYPE
DMA Write
DMA Read
I/O Read
I/O Write
LPC address/data bus. Multiplexed command, address and data bus.
Frame signal. Indicates start of new cycle and termination of broken cycle
PCI Reset. Used as LPC Interface Reset.
Encoded DMA/Bus Master request for the LPC interface.
Power Mgt Event signal. Allows the LPC47M14x to request wakeup.
Powerdown Signal. Indicates that the LPC47M14x should prepare for power to be shut
on the LPC interface.
Serial IRQ.
PCI Clock.
Page 21
DESCRIPTION
TRANSFER SIZE
1 Byte
1 Byte
1 byte
1 byte
Rev. 03/19/2001