LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 127

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

Note 1: This register is read-only when GP43 register bit [3:2] = 01 and the GP43 pin is high.
Note 2: Bits [3:2] of this register are reset (cleared) on VCC POR and Hard Reset (and VTR POR).
Note 3: Bit 3 of this register is reset (cleared) on VCC POR and Hard Reset (and VTR POR).
Note 4: The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared.
Note 5: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may be set on a
VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits will be
set on a VCC POR Also, GP32 and GP33 pins revert to their non-inverting GPIO input function when VCC is removed
from the part. These GPIOs cannot be used for PME wakeup when the part is under VTR power (VCC=0).
The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address
register for Logical Device A.
SMSC DS – LPC47M14X
REGISTER
OFFSET
60-7F
(hex)
5C
5D
5A
5B
5E
5F
PME_STS
Default = 0x00
on VTR POR
N/A
PME_EN
Default = 0x00
on VTR POR
N/A
NAME
TYPE
R/W
R/W
R/W
R/W
R/W
R
R
RESET
HARD
Table 59 – PME, SMI, GPIO, FAN Register Description
-
-
-
-
-
-
-
REG OFFSET
(R/W)
(R/W)
(hex)
(R)
(R)
00
01
02
03
VCC POR
-
-
-
-
-
-
-
Bit[0] PME_Status
= 0 (default)
= 1 Set when LPC47M14x would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET
or HARD RESET.
Writing a “1” to PME_Status will clear it and cause the
LPC47M14x to stop asserting nIO_PME, in enabled.
Writing a “0” to PME_Status has no effect.
Reserved – reads return 0
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or
HARD RESET
Reserved – reads return 0
VTR POR
Page 127
nIO_PME signal, independent of the state of the
PME_En bit.
0x00
0x00
0x00
0x00
0x00
0x00
nIO_PME signal assertion is disabled (default)
Enables LPC47M14x to assert nIO_PME signal
-
RESET
SOFT
DESCRIPTION
-
-
-
-
-
-
-
LED1
LED2
Reserved – reads return 0
Fan2 Tachometer Register
Fan1 Preload Register
Fan2 Preload Register
Keyboard Scan Code
REGISTER
Rev. 03/19/2001