LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 166

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

Note 1: To properly share and IRQ,
Note:
SMSC DS – LPC47M14X
Serial Port 1
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
Serial Port 2
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs
will assert when either UART generates an interrupt.
NAME
NAME
1. Configure UART1 (or UART2) to use the desired IRQ.
2. Configure UART2 (or UART1) to use No IRQ selected.
3. Set the share IRQ bit.
Table 70 – Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]
Table 71 – Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]
REG INDEX
REG INDEX
0xF0 R/W
0xF0 R/W
UART Interrupt Operation Table
Bit[0] MIDI Mode
= 0
= 1
Bit[1] High Speed
= 0
= 1
Bit[6:2] Reserved, set to zero
Bit[7]: Share IRQ
=0 UARTs use different IRQs
=1 UARTs share a common IRQ
See Note 1 below.
Bit[0] MIDI Mode
= 0
= 1
Bit[1] High Speed
= 0
= 1
Bit[4:2] Reserved, set to zero
Bit[5] TXD2_MODE (Note 1)
=0
=1
Bits[7:6] Reserved. Set to zero.
MIDI support disabled (default)
MIDI support enabled
High Speed Disabled(default)
High Speed Enabled
MIDI support disabled (default)
MIDI support enabled
High Speed disabled(default)
High Speed enabled
The inactive state of the TXD2 pin is low.
The inactive state of the TXD2 pin is tristate.
Page 166
DEFINITION
DEFINITION
STATE
STATE
C
C
Rev. 03/19/2001