EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 485

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Error Detection
Timing
Altera Corporation
October 2007
Table 15–6. Minimum and Maximum Error Detection Frequencies
Device Type
Stratix III
Error Detection
100 MHz / 2
Frequency
When the CRC feature is enabled through the Quartus II software, the
device automatically activates the CRC process upon entering user mode,
after configuration, and after initialization is complete.
The CRC_ERROR pin is always pulled low at the end of the error detection
cycle for a minimum of 31 cycles. Then it is pulled high at the end of the
error location search, if there is a CRAM bit error. If the new CRC
calculation does not contain any corrupted bits, the CRC_ERROR pin is
driven low. The error detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator
with a divisor that sets the maximum frequency.
minimum and maximum error detection frequencies.
You can set a lower clock frequency by specifying a division factor in the
Quartus II software (refer to
divisor is a power of two (2), where n is between 1 and 8. The divisor
ranges from 2 through 256. See the following equation:
You need to monitor the error message to avoid missing information in
the Error Message Register. The Error Message Register is updated
whenever an error or errors occur. The minimum interval time between
each update for the Error Message Register depends on the device and
JTAG Fault Injection
Register
Fault Injection Register
Table 15–5. Error Detection Registers (Part 2 of 2)
n
Error detection frequency
Detection Frequency
Register
Maximum Error
50 MHz
This 21-bit register is fully controlled by the JTAG
instruction
the information of the error injection that you want
in the bitstream.
The content of the JTAG Fault Injection Register is
loaded into this 21-bit register when it is being
updated.
=
“Software Support” on page
100MHz
-------------------- -
Detection Frequency
Minimum Error
2
n
EDERROR_INJECT
390 kHz
Stratix III Device Handbook, Volume 1
SEU Mitigation in Stratix III Devices
Description
Table 15–6
. This register holds
Valid Divisors (2
1, 2, 3, 4, 5, 6, 7, 8
15–12). The
shows the
15–11
n
)