EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 254

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

OCT Calibration
Figure 7–19. OCT User-Mode Signal Timing Waveform for One OCT Block
Note to
(1)
7–36
Stratix III Device Handbook, Volume 1
t
s2p
Figure
≥ 25ns
OCTUSRCLK
S2PENA_1A
nCLRUSR
7–19:
ENASER0
ENAOCT
After calibrated codes are shifted in serially to each I/O bank, the
calibrated codes must be converted from serial format to parallel format
before being used in the I/O buffers.
that can be asserted at any time to update the calibration codes in each
I/O bank. All I/O banks that received the codes from the same OCT
calibration block can have S2PENA asserted at the same time, or at a
different time, even while another OCT calibration block is calibrating
and serially shifting codes. The S2PENA signal is asserted one
OCTUSRCLK cycle after ENASER is deasserted for at least 25ns. You cannot
use I/Os for transmitting or receiving data when their S2PENA is asserted
for parallel codes transfer.
Example of Using Multiple OCT Calibration Blocks
Figure 7–20
blocks doing R
calibrating at different times by asserting ENASER signals at different
times. ENAOCT must stay asserted while any calibration is ongoing.
nCLRUSR must be set to low for one OCTUSRCLK cycle before each
ENASER[N] signal is asserted. In
for the second time to initialize OCT calibration block 0, this does not
affect OCT calibration block 1, whose calibration is already in progress.
(1000 OCTUSRCLK cycles)
Calibration Phase
shows a signal timing waveform for two OCT calibration
S
and R
T
calibration. Calibration blocks can start
Figure
OCTUSRCLK
Cycles
Figure 7–19
28
7–20, when nCLRUSR is set to 0
t s2p
shows S2PENA signals
(1)
Altera Corporation
November 2007