EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 191

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
You should assert the areset signal every time the PLL loses lock to
guarantee the correct phase relationship between the PLL input clock and
output clocks. You can set up the PLL to automatically reset (self reset)
upon a loss-of-lock condition using the Quartus II MegaWizard. You
should include the areset signal in designs if any of the following
conditions are true:
■
■
1
locked
The locked output of the PLL indicates that the PLL has locked onto the
reference clock and the PLL clock outputs are operating at the desired
phase and frequency set in the Quartus II software MegaWizard. Without
any additional circuitry, the lock signal may toggle as the PLL begins the
locking process. The lock detection circuit provides a signal to the core
logic that gives an indication if the feedback clock has locked onto the
reference clock both in phase and frequency.
1
Clock Switchover
The clock switchover feature allows the PLL to switch between two
reference input clocks. Use this feature for clock redundancy or for a
dual-clock domain application such as in a system that turns on the
redundant clock if the previous clock stops running. The design can
perform clock switchover automatically, when the clock is no longer
toggling or based on a user control signal, clkswitch.
The following clock switchover modes are supported in Stratix III PLLs:
■
PLL reconfiguration or clock switchover is enabled in the design.
Phase relationships between the PLL input and output clocks need to
be maintained after a loss-of-lock condition.
Automatic switchover: The clock sense circuit monitors the current
reference clock and if it stops toggling, automatically switches to the
other clock inclk0 or inclk1.
If the input clock to the PLL is not toggling or is unstable upon
power up, assert the areset signal after the input clock is stable
and within specifications.
Altera recommends that you use the areset and locked
signals in your designs to control and observe the status of your
PLL.
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
6–41