EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 103

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 5–1. Overview of DSP Block Signals
Simplified DSP
Operation
Altera Corporation
October 2007
Control
Input
Data
288
144
144
34
Each DSP block occupies four LAB blocks in height and can be divided
further into two half-blocks that share some common clock signals, but
are for all common purposes identical in functionality. The layout of each
block is shown in
1
In Stratix and Stratix II devices, the fundamental building block consists
of an 18-bit × 18-bit multiplier that can also function as two 9-bit × 9-bit
multipliers. For Stratix III, the fundamental building block is a pair of
18-bit × 18-bit multipliers followed by a first-stage 37-bit
addition/subtraction unit, as shown in
Note that for all signed numbers, input and output data is represented in
2’s complement format only.
Equation 5–1. Multiplier Equation
Full DSP Block
The Stratix III DSP block input data lines of 288 bits is double
that of Stratix and Stratix II, but the number of output data lines
remains at 144 bits.
P[36..0] = A
Figure
Half-DSP Block
Half-DSP Block
0
[17..0] × B
5–1.
0
[17..0] ± A
Stratix III Device Handbook, Volume 1
Equation 5–1
DSP Blocks in Stratix III Devices
1
[17..0] × B
72
72
and
1
[17..0]
Figure
5–2.
Output
Data
Output
Data
5–3