EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 281

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 8–3. Number of DQS/DQ Groups per Bank in EP3SE50, EP3SL50, and EP3SL70 Devices in 484-pin
FineLine BGA Package
Notes to
(1)
(2)
(3)
(4)
(5)
Altera Corporation
November 2007
Numbers are preliminary.
This device does not support ×32/×36 mode.
Some of the ×4 groups may use R
you use these pins as R
Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are
not going to be used by your configuration scheme.
All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n,
CLK10p, and CLK10n)
Figure
8–3:
26 User I/Os (5)
26 User I/Os (5)
I/O Bank 1A (3)
I/O Bank 1C (4)
I/O Bank 2A (3)
24 User I/Os
24 User I/Os
Notes
x16/x18=0
I/O Bank 2C
x16/x18=0
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
x8/x9=1
UP
x8/x9=1
DLL 1
x4=3
x4=3
DLL 2
x4=3
x4=3
and R
(1),
DN
(2)
UP
pins for OCT calibration.
/R
EP3SE50, EP3SL50, and EP3SL70 Devices
DN
24 User I/Os
24 User I/Os
I/O Bank 8C
I/O Bank 3C
x16/x18=0
x16/x18=0
pins as DQ pins. You would lose one DQS/DQ group (in any mode) if
x8/x9=1
x8/x9=1
x4=2
x4=2
484-pin FineLine BGA
24 User I/Os
I/O Bank 4C
24 User I/Os
I/O Bank 7C
External Memory Interfaces in Stratix III Devices
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
x4=3
x4=3
Stratix III Device Handbook, Volume 1
I/O Bank 6A (3)
26 User I/Os (5)
26 User I/Os (5)
I/O Bank 5A (3)
24 User I/Os
24 User I/Os
I/O Bank 6C
x16/x18=0
I/O Bank 5C
x16/x18=0
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
x8/x9=1
x8/x9=1
DLL 4
DLL 3
x4=3
x4=3
x4=3
x4=3
8–11