EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 465

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Introduction
Altera Corporation
October 2007
SIII51014-1.1
This chapter provides an overview of the design security feature and its
implementation on Stratix
standard (AES) as well as the security modes available in Stratix III
devices for designers to utilize this new feature in their designs.
As Stratix III devices start to play a role in larger and more critical designs
in competitive commercial and military environments, it is increasingly
important to protect the designs from copying, reverse engineering, and
tampering.
Stratix III devices address these concerns and are the industry's only
high-density and high-performance devices with both volatile and
non-volatile security feature support. Stratix III devices have the ability to
decrypt configuration bitstreams using the AES algorithm, an industry
standard encryption algorithm that is FIPS-197 certified. Stratix III
devices have a design security feature which utilizes a 256-bit security
key.
Altera
memory (SRAM) configuration cells during device operation. Because
the SRAM memory is volatile, the SRAM cells must be loaded with
configuration data each time the device powers-up. It is possible to
intercept configuration data when it is being transmitted from the
memory source (flash memory or a configuration device) to the device.
The intercepted configuration data could then be used to configure
another device.
When using the Stratix III design security feature, the security key is
stored in the Stratix III device. Depending on the security mode, you can
configure the Stratix III device using a configuration file that is encrypted
with the same key, or for board testing, configured with a normal
configuration file.
The design security feature is available when configuring Stratix III
devices using the fast passive parallel (FPP) configuration mode with an
external host (such as a MAX
using fast active serial (AS) or passive serial (PS) configuration schemes.
The design security feature is also available in remote update with fast AS
configuration mode. The design security feature is not available when
you are configuring your Stratix III device using FPP with an enhanced
®
Stratix III devices store configuration data in static random access
®
III devices using advanced encryption
®
14. Design Security in
II device or microprocessor), or when
Stratix III Devices
14–1