EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 161
EP3SL150F780I3N
Manufacturer Part Number
EP3SL150F780I3N
Description
Stratix III
Manufacturer
Altera
Datasheet
1.EP3SL110.pdf
(904 pages)
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Altera Corporation
November 2007
RCLK51
RCLK52
RCLK53
RCLK22
RCLK23
RCLK24
RCLK25
RCLK26
RCLK27
RCLK28
RCLK29
RCLK30
RCLK31
RCLK32
RCLK33
RCLK34
RCLK35
RCLK36
RCLK37
Table 6–4. Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 2) (Part 2 of 2)
Table 6–5. Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 3)
Clock Resource
Clock Resource
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1
1
Table 6–5
and RCLKs in device Quadrant 3. A given clock input pin can drive two
adjacent regional clock networks to create a dual-regional clock network.
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3
3
shows the connectivity between the dedicated clock input pins
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CLK (p/n Pins)
CLK (p/n Pins)
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Clock Networks and PLLs in Stratix III Devices
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Stratix III Device Handbook, Volume 1
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