EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 273

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Notes to
(1)
(2)
(3)
(4)
DDR2 SDRAM
DDR SDRAM
Table 8–2. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Full-Rate
Controller
Memory Standards
Numbers are preliminary until characterization is final.
DDR3 SDRAM, QDRII/QDRII+ SRAM, and RLDRAM II support will be evaluated for a future version of the
Quartus II software.
Performance is based on 0.9-V core voltage. At 1.1-V core voltage, the -4L speed grade devices have the same
performance as the -4 speed grade devices.
This applies for interfaces with both modules and components.
Table
Note
(4)
8–2:
(4)
(1),
(2)
I/O Banks
Bottom
–2 Speed Grade
Top/
267
200
Figure 8–1
support, showing the phase-locked loop (PLL), delay-locked loop (DLL),
and I/O banks. The number of available I/O banks and PLLs depend on
the device density.
(MHz)
Banks
Right
Left/
267
200
I/O
shows a package-bottom view for Stratix III external memory
I/O Banks
Bottom
–3 Speed Grade
Top/
233
200
(MHz)
External Memory Interfaces in Stratix III Devices
Banks
Right
Left/
233
200
I/O
Bottom
Stratix III Device Handbook, Volume 1
Banks
–4 Speed Grade
Top/
200
200
I/O
(MHz)
Banks
Right
Left/
200
200
I/O
-4L Speed Grade
Bottom
Banks
Top/
167
167
I/O
(MHz)
(3)
Banks
Right
Left/
167
167
I/O
8–3