EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 305

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 8–15. Stratix III DQS Postamble Circuitry
Note to
(1)
(2)
Altera Corporation
November 2007
The postamble clock can come from any of the delayed resynchronization clock taps although it is not necessarily
of the same phase as the resynchronization clock.
The dqsenable signal can also come from the Stratix III FPGA fabric.
Figure
8–15:
Resynchronization
Postamble
Postamble
Enable
Clock
Clock
In addition to the dedicated postamble register, Stratix III devices also
have an HDR block inside the postamble enable circuitry. These registers
are used if the controller is running at half the frequency of the I/Os.
The use of the HDR block as the first stage capture register in the
postamble enable circuitry block in
block is clocked by the half-rate resynchronization clock, which is the
output of the I/O Clock Divider circuit (shown in
an AND gate after the postamble register outputs that is used to avoid
postamble glitches from a previous read burst on a non-consecutive read
burst. This scheme allows a half-a-clock cycle latency for dqsenable
assertion and zero latency for dqsenable deassertion as shown in
Figure
8–16.
DQS Enable
B
D
Note (1)
Q
A
DQS'
gated_dqs control
External Memory Interfaces in Stratix III Devices
D
D
DQS Bus
Q
Q
Figure 8–15
Stratix III Device Handbook, Volume 1
reset
DFF
Q
PRN
CLR
dqsenable (2)
is optional. The HDR
D
Figure
V
CC
8–20). There is
8–35