M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 86

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R
R
M
e
E
1
. v
J
Figure 9.3.1. Interrupt Control Registers
6
BCNIC, DM0IC, DM1IC, KUPIC, ADIC, S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC TO
TB2IC, INT3IC, INT4IC, INT5IC, INT0IC to INT2IC
0
2
C
9
0 .
B
2 /
0
0
6
2
A
0
F
Interrupt control register
2
b7
b7
NOTES:
e
NOTES:
G
0 -
b
1. This bit can only be reset by writing “0” (Do not write “1”).
2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
3. If the IFSRi bit (i = 0 to 5) in the IFSR register is “1” (both edges), set the POL bit in the INTiIC register to “0” (falling
1 .
o r
b6
b6
1.This bit can only be reset by writing “0” (Do not write “1”).
2. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
2
0
For details, see 19.5 Interrupts.
edge).
, 5
register. For details, see 19.5 Interrupts.
u
0
b5
b5
0
p
2
0
(
b4
b4
M
0
7
1
b3
b3
6
C
b2
b2
page 67
2 /
b1
b1
6
, A
b0
b0
M
Bit symbol
Bit symbol
1
f o
(b7-b6)
(2)
(b7-b4)
ILVL0
ILVL1
ILVL2
6
ILVL0
ILVL1
ILVL2
POL
(b5)
C
IR
3
IR
BCNIC
DM0IC, DM1IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
INT3IC
INT5IC
INT4IC
INT0IC to INT2IC
2
2 /
9
Symbol
6
Symbol
, B
Interrupt priority level
select bit
Interrupt request bit
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
M
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
1
6
C
Bit name
Bit name
2 /
6
0044
0048
0049
005D
) T
Address
16
16
16
16
to 005F
004A
004B
004D
004E
0051
0052
0055
005A
Address
16
16
16
16
16
16
16
16
16
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
, 0053
, 0054
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Must always be set to “0”
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
, 004C
to 0059
to 005C
XX00X000
XX00X000
XX00X000
XX00X000
After reset
16
16
16
, 004F
, 0050
16
16
16
16
2
2
2
2
Function
Function
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
After reset
(3)
2
2
2
2
2
2
2
2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(1)
(1)
9. Interrupt