M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 10

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Quick Reference by Address _______________________ B-1
1. Overview ______________________________________ 1
2. Central Processing Unit (CPU) ____________________ 17
3. Memory ______________________________________ 19
4. Special Function Registers (SFRs) _________________ 20
1.1 Applications ................................................................................................................... 1
1.2 Performance Outline ..................................................................................................... 2
1.3 Block Diagram ............................................................................................................... 4
1.4 Product List ................................................................................................................... 6
1.5 Pin Assignments .......................................................................................................... 11
1.6 Pin Description ............................................................................................................ 15
2.1 Data Registers (R0, R1, R2 and R3) ........................................................................... 17
2.2 Address Registers (A0 and A1) ................................................................................... 17
2.3 Frame Base Register (FB) .......................................................................................... 18
2.4 Interrupt Table Register (INTB) ................................................................................... 18
2.5 Program Counter (PC) ................................................................................................ 18
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ...................................... 18
2.7 Static Base Register (SB) ........................................................................................... 18
2.8 Flag Register (FLG) .................................................................................................... 18
2.8.1 Carry Flag (C Flag) .............................................................................................. 18
2.8.2 Debug Flag (D Flag) ............................................................................................ 18
2.8.3 Zero Flag (Z Flag) ............................................................................................... 18
2.8.4 Sign Flag (S Flag) ................................................................................................ 18
2.8.5 Register Bank Select Flag (B Flag) ...................................................................... 18
2.8.6 Overflow Flag (O Flag) ......................................................................................... 18
2.8.7 Interrupt Enable Flag (I Flag) ............................................................................... 18
2.8.8 Stack Pointer Select Flag (U Flag) ....................................................................... 18
2.8.9 Processor Interrupt Priority Level (IPL) ................................................................ 18
2.8.10 Reserved Area ................................................................................................... 18
Table of Contents
A-1