M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 135

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R
R
M
e
E
. v
J
1
Figure 12.2.4.1 TBiMR Register in A/D Trigger Mode
Figure 12.2.4.2 TB2SC Register
0
6
2
9
C
0 .
B
0
2 /
0
2
6
0
F
A
2
e
0 -
Timer Bi mode register (i= 0 to 1)
Timer B2 special mode register
b7
b7
b
G
NOTE:
NOTES:
1 .
2
o r
b6
0
b6
1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
0
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to
4. Related pins are U(P8
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the
7. Refer to 16.6 Digital Debounce function for SD input.
, 5
0
u
"0" (timer B2 underflow).
"0" (= input mode).
pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.
If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).
At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1
bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those
pins is used.
INV02 bit to "1" (three-phase motor control timer function).
b5
0
b5
2
p
0
b4
(
0
b4
M
7
b3
1
b3
6
b2
page 116
C
b2
b1
2 /
b1
0
6
b0
, A
b0
0
0
Bit symbol
), U(P8
IVPCR1
TB2SEL
(b6-b5)
PWCOM
TB0EN
M
TB1EN
Bit symbol
(b7)
f o
Symbol
TB2SC
1
TMOD0
TMOD1
TCK0
TCK1
MR0
MR1
MR2
MR3
6
TB0MR to TB1MR
3
1
C
2
), V(P7
9
2 /
Timer B0 Operation Mode
Select Bit
Three-Phase Output Port
SD Control Bit 1
Timer B1 Operation Mode
Select Bit
Symbol
Timer B2 Reload Timing
Switch Bit
Trigger Select Bit
Reserved bits
(1)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
6
, B
2
), V(P7
When write in A/D trigger mode, set to “0”. When read in A/D
trigger mode, its content is indeterminate.
Operation Mode Select Bit
Invalid in A/D trigger mode
Either "0" or "1" is enabled
TB0MR register
TB1MR register
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
Count Source Select Bit
Address
Set to “0” in A/D trigger mode
039E
M
Bit name
1
(2)
3
16
6
), W(P7
(3, 4, 7)
C
Bit name
2 /
(6)
039B
6
4
), W(P7
) T
(1)
Address
16
to 039C
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
0 : Three-phase output forcible cutoff
1 : Three-phase output forcible cutoff
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : Other than A/D trigger mode
1 : A/D trigger mode
X0000000
5
After reset
Must set to "0"
). When a high-level ("H") signal is applied to the SD
generation frequency setting counter [ICTB2]
by SD pin input (high impedance)
disabled
by SD pin input (high impedance)
enabled
16
0 0 : Timer mode or A/D trigger mode
0 0 : f
0 1 : f
1 0 : f
1 1 : f
b1 b0
b7 b6
2
1
8
32
C32
00XX0000
or f
After reset
Function
2
(5)
(5)
Function
2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
12. Timer