HW-V5-ML555-G Xilinx Inc, HW-V5-ML555-G Datasheet - Page 55

• Manufacturer Part Number: HW-V5-ML555-G
• Description: BOARD EVAL FOR VIRTEX-5 ML555
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-ML555-G

• Contents: Board, Cables, CD
• Silicon Manufacturer: Xilinx
• Features: Parallel Connectivity, Three On-board Clock Sources
• Kit Contents: Board, Cables, CD, Power Supply
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-1FF1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 FPGA
• For Use With: HW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-EPHY - DAUGHTER CARD PHY BERG-EPHY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1586; HW-V5-ML555-G

Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
P13-A13
P13-A14
125 MHz
P1-B16
10 MHz
25 MHz
J10
J11
J12
J13
FPGA_GCLK_30MHZ
R
SMA_GCLKP
SMA_GCLKN
SMA
SMA
PCICLK
200 MHz
LVPECL
Figure 3-8: Clock Synthesis Block Diagram (Default Configuration)
Driver
Clock
Synth
Clock
Synth
Clock
PCIE_REFCLK
4.7KΩ
#1
#2
Figure 3-8
production ML555 boards.
2.5V
0
1
0
1
0
1
shows a block diagram of the default clock synthesis configuration, provided on
LVPECL_200M_P
LVPECL_200M_N
1
0
MGT_X0Y1_RCLKP
MGT_X0Y1_RCLKN
MGT_X0Y0_RCLKP
MGT_X0Y0_RCLKN
Clock
Driver
Clock
Select
Mux
DC Block
Capacitors
Q0
Q1
0
1
www.xilinx.com
SFP_MGT_GCLKP
SFP_MGT_GCLKN
SFP_MGT_REFCLKP
SFP_MGT_REFCLKN
SATA_MGT_GCLKP
SATA_MGT_GCLKN
SATA_MGT_REFCLKP
SATA_MGT_REFCLKN
SATA_MGT_CLKSEL
H17
H18
H19
H20
AF4
AF3
G15
G16
H15
AL5
AL4
K17
L19
L18
J20
J21
J14
Y4
Y3
P4
P3
H4
H3
E4
D4
GCLK
GCLKP
GCLKN
MGT_REFCLKP
MGT_REFCLKN
GCLKP
GCLKN
MGT_REFCLKP
MGT_REFCLKN
MGT_REFCLKP
MGT_REFCLKN
MGT_REFCLKP
MGT_REFCLKN
GCLKP
GCLKN
MGT_REFCLKP
MGT_REFCLKN
GCLKP
GCLKN
MGT_REFCLKP
MGT_REFCLKN
Bank 3 I/O
GCLKP
GCLKN
GCLK
U10 FPGA
GTP X0Y2
GTP X0Y1
GTP X0Y0
GTP X0Y3
GTP X0Y4
GTP X0Y5
Clock Generation
UG201_c3_18_022608
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