XC95288XL-6BG256C XILINX [Xilinx, Inc], XC95288XL-6BG256C Datasheet

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XC95288XL-6BG256C

Manufacturer Part Number
XC95288XL-6BG256C
Description
XC95288XL High Performance CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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DS055 (v1.5) June 20, 2002
Features
Description
The XC95288XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
DS055 (v1.5) June 20, 2002
Product Specification
6 ns pin-to-pin logic delays
System frequency up to 208 MHz
288 macrocells with 6,400 usable gates
Available in small footprint packages
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Optimized for high-performance 3.3V systems
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Advanced system features
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Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
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Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
144-pin TQFP (117 user I/O pins)
208-pin PQFP (168 user I/O pins)
256-pin BGA (192 user I/O pins)
256-pin FBGA (192 user I/O pins)
280-pin CSP (192 user I/O pins)
Low power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
In-system programmable
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Endurance exceeding 10,000 program/erase
cycles
20 year data retention
ESD protection exceeding 2,000V
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
1-800-255-7778
5
XC95288XL High Performance
CPLD
Product Specification
propagation delays of 6 ns. See
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
used:
where:
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
value varies with the design application and should be veri-
fied during normal system operation.
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note
CPLD Power.”
I
CC
Figure 1: Typical I
(mA) = MC
MC
PT
per macrocell
MC
PT
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
HS
LP
150
100
HS
LP
550
500
450
400
350
300
250
200
50
+ 0.272) + 0.04 * MC
0
= average number of low power product terms per
= average number of high-speed product terms
= # macrocells in low power configuration
= # macrocells in high-speed configuration
HS
(0.175*PT
XAPP114, “Understanding XC9500XL
50
CC
Clock Frequency (MHz)
vs. Frequency for XC95288XL
CC
HS
100
94 MHz
, the following equation may be
TOG
+ 0.345) + MC
(MC
Figure 2
150
HS
Figure 1
+MC
for architecture
LP
200
DS055_01_121501
LP
(0.052*PT
208 MHz
)* f
shows the
250
LP
CC
1

Related parts for XC95288XL-6BG256C

XC95288XL-6BG256C Summary of contents

Page 1

... Pin-compatible with 5V-core XC95288 device in the 208-pin HQFP package Description The XC95288XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...

Page 2

... JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 4 I/O/GTS Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95288XL Architecture www.xilinx.com 1-800-255-7778 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...

Page 3

... GND Max GND Max Max; CC CCIO V = GND or 3. Min < V < 5. GND 1.0 MHz GND, No load 1.0 MHz IN www.xilinx.com 1-800-255-7778 XC95288XL High Performance CPLD Value –0.5 to 4.0 –0.5 to 5.5 –0.5 to 5.5 –65 to +150 +260 +150 Min Max 3.0 3 3.0 3.6 3.0 3.6 2.3 2.7 0 0.80 2.0 5 ...

Page 4

... XC95288XL High Performance CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input PSU T I/O hold time after p-term clock input ...

Page 5

... Fast CONNECT II feedback delay F Time Adders T Incremental product term allocator delay PTA (first incremental delay) T Incremental product term allocator delay PTA2 (subsequent incremental delay) T Slew-rate limited delay SLEW DS055 (v1.5) June 20, 2002 Product Specification XC95288XL High Performance CPLD XC95288XL-6 XC95288XL-7 Min Max Min Max - 2.2 - 2.3 - 1 ...

Page 6

... XC95288XL High Performance CPLD XC95288XL I/O Pins Func- tion Macro- Block cell TQ144 PQ208 BG256 FG256 CS280 1 1 – – – – – – – – – – – ...

Page 7

... C4 C4 549 8 15 – – 546 543 8 17 – – 540 8 18 www.xilinx.com 1-800-255-7778 XC95288XL High Performance CPLD TQ144 PQ208 BG256 FG256 CS280 – – – – – – – – – – – ...

Page 8

... XC95288XL High Performance CPLD XC95288XL I/O Pins (Continued) Func- tion Macro- Block cell TQ144 PQ208 BG256 FG256 CS280 9 1 – – – Y11 W11 9 4 – – – V11 U11 9 7 – – – ...

Page 9

... B16 D17 111 16 17 – – 108 16 18 www.xilinx.com 1-800-255-7778 XC95288XL High Performance CPLD TQ144 PQ208 BG256 FG256 CS280 – – – – – 79 117 P19 M12 P16 80 118 P20 M16 P19 – – – ...

Page 10

... XC95288XL High Performance CPLD XC95288XL Global, JTAG and Power Pins Pin Type TQ144 I/O/GCK1 30 I/O/GCK2 32 I/O/GCK3 38 I/O/GTS1 5 I/O/GTS2 6 I/O/GTS3 2 I/O/GTS4 3 I/O/GSR 143 TCK 67 TDI 63 TDO 122 TMS 65 V 3.3V 8, 42, 84, 141 CCINT V 2.5V/3 37, 55, 73, 109, CCIO 127 GND 18, 29, 36, 47, 62, ...

Page 11

... Added -7 speed and CS280 package. 02/08/01 1.3 Updated -6 AC and timing parameters, added FG256 package. 03/19/01 1.4 Pinout corrections. 06/20/02 1.5 Updated I Added additional I DS055 (v1.5) June 20, 2002 Product Specification XC95288XL -6 TQ 144 C Package Array (FBGA) 144 208 256 Plastic PQFP Plastic BGA TQ44 PQ208 BG256 ...

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