HW-V5-ML555-G Xilinx Inc, HW-V5-ML555-G Datasheet - Page 24

• Manufacturer Part Number: HW-V5-ML555-G
• Description: BOARD EVAL FOR VIRTEX-5 ML555
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-ML555-G

• Contents: Board, Cables, CD
• Silicon Manufacturer: Xilinx
• Features: Parallel Connectivity, Three On-board Clock Sources
• Kit Contents: Board, Cables, CD, Power Supply
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-1FF1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 FPGA
• For Use With: HW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-EPHY - DAUGHTER CARD PHY BERG-EPHY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1586; HW-V5-ML555-G

Chapter 3: Hardware Description
24
Table 3-1
supports x1, x4, and x8 endpoint designs. The ML555 board is an endpoint add-in card.
Port names are with respect to the system board host.
Table 3-1: P13 Edge Connector Socket Pinout for PCI Express Designs
P13 A Side
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A1
A2
A3
A4
A5
A6
A7
A8
A9
shows the connector pin assignment for PCI Express designs. The board
PCIE_PRSNT1_B
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_PERST
www.xilinx.com
JTAG_TDO
JTAG_TCK
JTAG_TMS
JTAG_TDI
RESERVED
+3.3 VOLTS
+3.3 VOLTS
+12 VOLTS
+12 VOLTS
PERN0
PERP0
PERN1
PERN2
Signal
PERP1
PERP2
PERP3
GND
GND
GND
GND
GND
GND
GND
GND
GND
KEY
(5)
(5)
(2)
(2)
(2)
(2)
(6)
(3)
(3)
(1)
P13 B Side
Virtex-5 FPGA ML555 Development Kit
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B1
B2
B3
B4
B5
B6
B7
B8
B9
UG201 (v1.4) March 10, 2008
PCIE_PRSNT2_B
+3.3 VOLTSAUX
PCIE_WAKE_B
JTAG_TRST_B
+3.3 VOLTS
RESERVED
+12 VOLTS
+12 VOLTS
+12 VOLTS
SMDAT
SMCLK
PETN0
PETP0
PETN1
PETN2
PETN3
Signal
PETP1
PETP2
PETP3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
KEY
(4)
(4)
(2)
(2)
(2)
(2)
(2)
(1)
R