HW-V5-ML555-G Xilinx Inc, HW-V5-ML555-G Datasheet - Page 100

• Manufacturer Part Number: HW-V5-ML555-G
• Description: BOARD EVAL FOR VIRTEX-5 ML555
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-ML555-G

• Contents: Board, Cables, CD
• Silicon Manufacturer: Xilinx
• Features: Parallel Connectivity, Three On-board Clock Sources
• Kit Contents: Board, Cables, CD, Power Supply
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-1FF1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 FPGA
• For Use With: HW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-EPHY - DAUGHTER CARD PHY BERG-EPHY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1586; HW-V5-ML555-G

Chapter 4: Configuration
SelectMAP Clock Selection
100
The default configuration of the ML555 board is to provide Master SelectMAP
configuration with the FPGA providing the configuration clock (CCLK) to both the FPGA
and Platform Flash devices. Slave SelectMAP configuration is not supported on the
ML555.
Table 4-1
the Mode Switch SW5.
Table 4-7: SelectMAP Clock Mode
Figure 4-8
Notes:
1. Xilinx recommends using an FPGA configuration clock frequency of 20 MHz rather than the default
Master SelectMAP
Y2 30 MHz
Oscillator
2 MHz CCLK used by the BitGen application. Refer to
Programming,” page 101
Mode
shows the Virtex-5 FPGA configuration mode along with the correct setting for
shows the clock structure for SelectMAP mode along with Header (P2).
U4 Clock Buffer
U1/U15 Flash
Master SelectMAP (default)
Table 4-7
CLKOUT
Figure 4-8: SelectMAP Clock Circuitry
FPGA CCLK drives Platform Flash CLKIN
for a BitGen example.
www.xilinx.com
CLKIN
shows the P2 connections for the CCLK source.
Function
“Platform Flash Image Generation and
1
3
5
P2 Header
Virtex-5 FPGA ML555 Development Kit
2
4
6
UG201 (v1.4) March 10, 2008
(1)
Header P2 Jumper
I/O/GC1
CCLK
GC
Settings
U10 FPGA
UG201_c4_08_022608
U6 CPLD
1-2
R