R0K561668S000BE Renesas Electronics America, R0K561668S000BE Datasheet - Page 918

• Manufacturer Part Number: R0K561668S000BE
• Description: KIT STARTER FOR H8SX/1668
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of R0K561668S000BE

• For Use With/related Products: H8SX/1668
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Section 3 Processing States
3.3.2
After the RES pin has gone low and the reset state has been entered, reset exception handling
starts when the RES pin goes high again.
When reset exception handling starts, the CPU fetches a start address (vector) from the exception
vector table and starts program execution from that start address. All interrupts, including NMI,
are disabled during reset exception handling and after it ends.
3.3.3
There are two types of illegal instructions: illegal general instructions and illegal slot instructions.
These illegal instructions must not be executed.
When the CPU detects the execution of an undefined instruction, illegal general instruction
exception handling starts. At this time, detection is not performed for fields that do not affect the
instruction definition, such as the EA extension and register fields. If an illegal general instruction
consists of multiple words, it may be detected during execution of the illegal instruction (2nd word
or later). Therefore, the operation results for the execution of an undefined instruction are not
guaranteed.
When an instruction which consists of multiple words or modifies the PC contents (branch, branch
with bit condition, TRAPA, or RTE instruction) is executed as a delay slot instruction (placed
immediately after a delayed branch instruction), illegal slot instruction exception handling starts.
When the exception handling for an illegal general instruction or an illegal slot instruction starts,
the CPU refers to the SP contents (ER7) and pushes the PC and CCR contents onto the stack.
Next, the CPU fetches the start address (vector) from the exception vector table and execution
branches to that start address to execute the program. The PC contents to be saved vary depending
on the execution state.
The contents of general registers including SP after the execution of an illegal general instruction
or illegal slot instruction are not guaranteed. The RTE instruction should not be used when exiting
the routine of the illegal instruction exception handling.
Rev. 4.00 Sep. 18, 2008 Page 900 of 914
REJ09B0102-0400
Reset Exception Handling
Illegal Instruction