R0K561668S000BE Renesas Electronics America, R0K561668S000BE Datasheet - Page 59

• Manufacturer Part Number: R0K561668S000BE
• Description: KIT STARTER FOR H8SX/1668
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of R0K561668S000BE

• For Use With/related Products: H8SX/1668
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 1.13 Absolute Address Access Ranges
1.8.7
The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the
instruction code.
This addressing mode has short formats in which 3- or 4-bit immediate data can be used.
When the size of immediate data is less than that of the destination operand value (byte, word, or
longword) the immediate data is zero-extended.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit
number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code,
for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction
code, for specifying a vector address.
1.8.8
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,
which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of
the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC
contents. The PC contents to which the displacement is added is the address of the first byte of the
next instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or
−32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting
Absolute
Address
Data area
Program area 24 bits
Immediate—#xx
Program-Counter Relative—@(d:8, PC) or @(d:16, PC):
8 bits
(@aa:8)
16 bits
(@aa:16)
32 bits
(@aa:32)
(@aa:24)
32 bits
(@aa:32)
Normal
Mode
A consecutive 256-byte area (the upper address is set in SBR)
H'0000 to
H'FFFF
Middle
Mode
H'000000 to
H'007FFF,
H'FF8000 to
H'FFFFFF
H'000000 to
H'FFFFFF
Rev. 4.00 Sep. 18, 2008 Page 41 of 914
Advanced
Mode
H'00000000 to
H'00FFFFFF
H'FFFF8000 to H'FFFFFFFF
H'00000000 to H'00007FFF,
H'00000000 to H'FFFFFFFF
H'00000000 to H'00FFFFFF
Maximum
Mode
H'00000000 to
H'FFFFFFFF
REJ09B0102-0400
Section 1 CPU