R0K561668S000BE Renesas Electronics America, R0K561668S000BE Datasheet - Page 33

• Manufacturer Part Number: R0K561668S000BE
• Description: KIT STARTER FOR H8SX/1668
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of R0K561668S000BE

• For Use With/related Products: H8SX/1668
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

1.5.4
EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0).
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions.
For details, see the hardware manual for the corresponding product.
1.5.5
VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are
read as 0s. This register is a base address of the vector area for exception handlings other than a
reset and a CPU address error (extended memory indirect is also out of the target). The initial
value is H'00000000. The VBR contents are changed with the LDC and STC instructions.
1.5.6
SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In
8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The
initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions.
1.5.7
MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists
of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the
Bit
7
6 to 3
2
1
0
Bit Name
T
—
I2
I1
I0
Extended Control Register (EXR)
Vector Base Register (VBR)
Short Address Base Register (SBR)
Multiply-Accumulate Register (MAC)
Initial
Value
0
All 1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Description
Trace Bit
When this bit is set to 1, a trace exception is
generated each time an instruction is executed.
When this bit is cleared to 0, instructions are
executed in sequence.
Reserved
These bits are always read as 1.
Interrupt Mask Bits
These bits designate the interrupt mask level (0 to
7).
Rev. 4.00 Sep. 18, 2008 Page 15 of 914
REJ09B0102-0400
Section 1 CPU