SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 49

• Manufacturer Part Number: SI5325/26-EVB
• Description: BOARD EVAL FOR SI5325/26
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5325/26-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5325, SI5326
• Processor To Be Evaluated: Si5325 and Si5326
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7. Recommended PCB Layout
Notes (General):
Notes (Solder Mask Design):
Notes (Stencil Design):
Notes (Card Assembly):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad.
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
based on a Fabrication Allowance of 0.05 mm.
pad is to be 60 µm minimum, all the way around the pad.
solder paste release.
Components.
Dimension
GE
GD
D2
ZE
ZD
E2
E
D
X
Y
e
Table 7. PCB Land Pattern Dimensions
Figure 5. PCB Land Pattern Diagram
Preliminary Rev. 0.4
4.00
4.00
4.53
4.53
MIN
—
—
—
0.50 BSC.
5.42 REF.
5.42 REF.
0.89 REF.
MAX
4.20
4.20
0.28
6.31
6.31
—
—
Si5325
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