SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 21

BOARD EVAL FOR SI5325/26

SI5325/26-EVB

Manufacturer Part Number
SI5325/26-EVB
Description
BOARD EVAL FOR SI5325/26
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5325/26-EVB

Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5325, SI5326
Processor To Be Evaluated
Si5325 and Si5326
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Reset value = 0000 0000
Reset value = 0100 0000
Register 10.
Register 11.
Name
Name
Type
Type
Bit
Bit
7:4
1:0
7:2
Bit
Bit
3
2
1
0
DSBL2_REG DSBL2_REG.
DSBL1_REG DSBL1_REG.
Reserved
Reserved
Reserved
PD_CK2
PD_CK1
Name
Name
D7
D7
Reserved.
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the NC2 output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the NC1 output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
Reserved.
Reserved.
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
D6
D6
Reserved
R
D5
D5
Reserved
R
Preliminary Rev. 0.4
D4
D4
DSBL2_
Function
Function
REG
R/W
D3
D3
DSBL1_
REG
R/W
D2
D2
Reserved
PD_CK2
R/W
D1
D1
R
Si5325
Reserved
PD_CK1
R/W
D0
D0
R
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