SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 42

• Manufacturer Part Number: SI5325/26-EVB
• Description: BOARD EVAL FOR SI5325/26
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5325/26-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5325, SI5326
• Processor To Be Evaluated: Si5325 and Si5326
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5325
Reset value = 0000 0000
42
Register 136.
Name RST_REG
Type
Bit
5:2
1:0
Bit
7
6
GRADE_RO
RST_REG
Reserved
R/W
Name
D7
ICAL
[1:0]
Internal Reset (Same as Pin Reset).
Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibration is
complete once the LOL alarm goes low. A valid stable clock (within 100 ppm) must be
present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take
effect.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibra-
tion, LOL will go low.
Reserved.
Indicates Maximum Clock Output Frequency of this Device.
Limits the range of the N1_HS divider.
00: N1_HS x NCn_LS > 4. Maximum clock output frequency = 1.4175 GHz.
01: N1_HS x NCn_LS > 6. Maximum clock output frequency = 808 MHz.
10: N1_HS x NCn_LS > 14. Maximum clock output frequency = 346 MHz.
11: N1_HS x NCn_LS > 20. Maximum clock output frequency = 243 MHz.
ICAL
R/W
D6
D5
Preliminary Rev. 0.4
D4
Reserved
R
Function
D3
D2
GRADE_RO [1:0]
D1
R
D0