SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 11

• Manufacturer Part Number: SI5325/26-EVB
• Description: BOARD EVAL FOR SI5325/26
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5325/26-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5325, SI5326
• Processor To Be Evaluated: Si5325 and Si5326
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5325 Register Map.
GND PAD
Pin #
22
23
25
24
26
27
29
28
34
35
36
SDA_SDO
Pin Name
CKOUT1–
CKOUT1+
CKOUT2–
CKOUT2+
CMODE
A2_SS
GND
SCL
SDI
A1
A0
Table 3. Si5325 Pin Descriptions (Continued)
GND
I/O
I/O
O
O
I
I
I
I
I
Signal Level
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Supply
Multi
Multi
Preliminary Rev. 0.4
Serial Clock/Serial Clock.
This pin functions as the serial clock input for both SPI and
I
This pin has a weak pulldown.
Serial Data.
In I
bidirectional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the
serial data output.
Serial Port Address.
In I
hardware controlled address bits. The I
[A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
This pin has a weak pulldown.
Serial Port Address/Slave Select.
In I
hardware controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the
slave select input.
This pin has a weak pulldown.
Serial Data In.
In I
In SPI control mode (CMODE = 1), this pin functions as the
serial data input.
This pin has a weak pulldown.
Output Clock 1.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock out-
puts.
Output Clock 2.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock out-
puts.
Control Mode.
Selects I
0 = I
1 = SPI Control Mode.
Must not float.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
2
C modes.
2
2
2
2
C control mode (CMODE = 0), this pin functions as the
C control mode (CMODE = 0), these pins function as
C control mode (CMODE = 0), this pin functions as a
C control mode (CMODE = 0), this pin is ignored.
2
C Control Mode.
2
C or SPI control mode for the Si5325.
Description
2
C address is 1101
Si5325
11