SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 15

BOARD EVAL FOR SI5325/26

SI5325/26-EVB

Manufacturer Part Number
SI5325/26-EVB
Description
BOARD EVAL FOR SI5325/26
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5325/26-EVB

Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5325, SI5326
Processor To Be Evaluated
Si5325 and Si5326
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Reset value = 1110 0100
Reset value = 0100 0010
Register 1.
Register 2.
Name
Name
Type
Type
Bit
Bit
7:4
3:2
1:0
7:4
3:0
Bit
Bit
BWSEL_REG
CK_PRIOR2
CK_PRIOR1
Reserved
Reserved
Name
Name
D7
D7
[1:0]
[1:0]
[3:0]
Reserved.
CK_PRIOR 2.
Selects which of the input clocks will be 2nd priority in the autoselection state machine.
00: CKIN1 is 2nd priority.
01: CKIN2 is 2nd priority.
10: Reserved
11: Reserved
CK_PRIOR 1.
Selects which of the input clocks will be 1st priority in the autoselection state machine.
00: CKIN1 is 1st priority.
01: CKIN2 is 1st priority.
10: Reserved
11: Reserved
BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to take
effect.
Reserved.
BWSEL_REG [3:0]
D6
D6
Reserved
R/W
R
D5
D5
Preliminary Rev. 0.4
D4
D4
Function
Function
CK_PRIOR2 [1:0]
D3
D3
R/W
D2
D2
Reserved
R
CK_PRIOR1 [1:0]
D1
D1
Si5325
R/W
D0
D0
15

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