SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 18

• Manufacturer Part Number: SI5325/26-EVB
• Description: BOARD EVAL FOR SI5325/26
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5325/26-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5325, SI5326
• Processor To Be Evaluated: Si5325 and Si5326
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5325
Reset value = 0010 1101
18
Register 6.
Name
Type
Bit
5:3
2:0
Bit
7
6
Reserved
SFOUT2_
SFOUT1_
REG [2:0]
REG [2:0]
Reserved
SLEEP
Name
D7
R
SLEEP
Reserved.
SLEEP.
In sleep mode, all clock outputs are disabled and the maximum amount of internal cir-
cuitry is powered down to reduce power dissipation and noise generation. This bit over-
rides the SFOUTn_REG[2:0] output signal format settings.
0: Normal operation
1: Sleep mode
SFOUT2_REG [2:0].
Controls output signal format and disable for CKOUT2 output buffer. Bypass mode is not
supported for CMOS output clocks.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
SFOUT1_REG [2:0].
Controls output signal format and disable for CKOUT1 output buffer. Bypass mode is not
supported for CMOS output clocks.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
R/W
D6
D5
SFOUT2_REG [2:0]
Preliminary Rev. 0.4
R/W
D4
Function
D3
D2
SFOUT1_REG [2:0]
R/W
D1
D0