SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 4

BOARD EVAL FOR SI5325/26

SI5325/26-EVB

Manufacturer Part Number
SI5325/26-EVB
Description
BOARD EVAL FOR SI5325/26
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5325/26-EVB

Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5325, SI5326
Processor To Be Evaluated
Si5325 and Si5326
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Si5325
Table 1. Performance Specifications
(V
4
Temperature Range
Supply Voltage
Supply Current
Input Clock Frequency
(CKIN1, CKIN2)
Output Clock Frequency
(CKOUT1, CKOUT2)
Input Clocks (CKIN1, CKIN2)
Input Voltage Level Limits
Differential Voltage Swing
Common Mode Voltage
Rise/Fall Time
(Minimum Pulse Width)
Output Clocks (CKOUT1, CKOUT2)
Common Mode
Differential Output Swing
Single Ended Output
Swing
Rise/Fall Time
Duty Cycle Uncertainty
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Frequency
Duty Cycle
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
Precision Clock Family Reference Manual. This document can be downloaded from
Documentation)
Parameter
.
CKN
CKN
CKN
CKO
Symbol
CKN
CKN
CKO
CK
V
CK
V
V
V
I
OCM
T
DD
DD
OD
SE
A
OF
VCM
DPP
TRF
TRF
VIN
F
DC
DC
ers. Consult Silicon Laboratories
for a given input frequency/clock
multiplication ratio combination.
Input frequency and clock multi-
A
programming device PLL divid-
configuration software DSPLL-
determine PLL divider settings
Line-to-Line Measured at 50%
sim at
plication ratio determined by
= –40 to 85 ºC)
(click on Documentation) to
Both CKOUTs enabled
Both CKOUTs enabled
LVPECL format output
CMOS format output
Whichever is smaller
f
CKOUT2 disabled
CKOUT2 disabled
OUT
f
Differential 100 
Preliminary Rev. 0.4
OUT
www.silabs.com/timing
Test Condition
Disable Mode
2.5 V ±10%
3.3 V ±10%
100  load
1.8 V ±5%
line-to-line
= 622.08 MHz
LVPECL
20–80%
20–80%
= 19.44 MHz
LVPECL
point
V
DD
1213
2.97
2.25
1.71
.002
0.25
Min
–40
970
–40
0.9
1.0
1.1
1.1
0.5
10
40
– 1.42
0
2
www.silabs.com/timing
Typ
251
217
204
194
165
230
3.3
2.5
1.8
25
V
DD
1134
1400
Max
3.63
2.75
1.89
1.95
0.93
V
279
243
234
220
710
945
350
1.4
1.7
1.9
85
11
60
40
– 1.25
DD
(click on
Unit
MHz
MHz
V
mA
mA
mA
mA
mA
ºC
ns
ns
ps
ps
%
V
V
V
V
V
V
V
V
V
V
PP

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