ATAVRMC321 Atmel, ATAVRMC321 Datasheet - Page 68

• Manufacturer Part Number: ATAVRMC321
• Description: KIT EVAL MOTOR CTRL LOW COST
• Manufacturer: Atmel
• Series: AVR®r

Specifications of ATAVRMC321

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATtinyx61
• Primary Attributes: 3-Ph BLDC, Brushed DC, Stepper Motor- Controller Board
• Secondary Attributes: Includes ATAVRMC300 Power Driver Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

68
ATtiny261/461/861
• Port B, Bit 1 – MISO/ DO/ OC1A/ PCINT9
• Port B, Bit 0 – MOSI/ DI/ SDA/ OC1A/ PCINT8
Table 10-7
shown in
Table 10-7.
Note:
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
• DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output
• OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the
• PCINT9: Pin Change Interrupt source 9.
• DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port
• SDA: Two-wire mode Serial Interface Data.
• OC1A: Inverted Output Compare Match output: The PB0 pin can serve as an external output
• PCINT8: Pin Change Interrupt source 8.
overrides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one).
PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one).
Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin
is also the output pin for the PWM mode timer function.
functions, so pin must be configure as an input for DI function.
for the Timer/Counter1 Compare Match B when configured as an output (DDB0 set). The
OC1A pin is also the inverted output pin for the PWM mode timer function.
1. “1” when the Fuse is “0” (Programmed).
Figure 10-5 on page
PB7/RESET/
dW/ADC10/
PCINT15
RSTDISBL
DWEN
1
RSTDISBL
DWEN
debugWire Transmit
0
0
0
0
ADC10D
PCINT15
RESET / ADC10
and
Overriding Signals for Alternate Functions in PB7:PB4
Table 10-8
(1)
(1)
(1)
(1)
•
•
relate the alternate functions of Port B to the overriding signals
61.
PB6/ADC9/T0/
INT0/PCINT14
0
0
0
0
0
0
0
RSTDISBL + (PCINT5
• PCIE + ADC9D)
ADC9D
T0/INT0/PCINT14
ADC9
PB5/XTAL2/CLKO/
OC1D/ADC8/
PCINT13
INTRC • EXTCLK
0
INTRC • EXTCLK
0
OC1D Enable
OC1D
0
INTRC • EXTCLK +
PCINT4 • PCIE +
ADC8D
(INTRC • EXTCLK) +
ADC8D
PCINT13
XTAL2, ADC8
(1)
PB4/XTAL1/
OC1D/ADC7/
PCINT12
INTRC
0
INTRC
0
OC1D Enable
OC1D
0
INTRC + PCINT12 •
PCIE + ADC7D
INTRC • ADC7D
PCINT12
XTAL1, ADC7
2588E–AVR–08/10
(1)