MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet - Page 9

• Manufacturer Part Number: MT4VDDT3232UY-6K1
• Description: MODULE DDR 128MB 167MHZ 172-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3232UY-6K1

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 333MT/s
• Package / Case: 172-UDIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 700mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6:
NOTE:
Table 7:
pdf: 09005aef808da768, source: 09005aef808d2e9a
DD4C16_32x32UG.fm - Rev. D 9/04 EN
LENGTH
1. For a burst length of two, A1–A9 select the two-data-
2. For a burst length of four, A2–A9 select the four-data-
3. For a burst length of eight, A3–A9 select the eight-
4. Whenever a boundary of the block is reached within a
BURST
element block; A0 selects the first access within the
block.
element block; A0–A1 select the first access within the
block.
data-element block; A0–A2 select the first access within
the block.
given sequence above, the following access wraps
within the block.
2
4
8
SPEED
-75Z
-75
-6
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
75
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLOCK FREQUENCY (MHZ)
CL = 2
ALLOWABLE OPERATING
N/A
N/A
ORDER OF ACCESSES WITHIN
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
f
SEQUENTIAL
100
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
A BURST
75
75
75
INTERLEAVED
CL = 2.5
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
f 167
f 133
f 133
0-1
1-0
9
Operating Mode
MODE REGISTER SET command with bits A7–A11
(64MB) or A7–A12 (128MB) each set to zero, and bits
A0-A6 set to the desired values. A DLL reset is initiated
by issuing a MODE REGISTER SET command with bits
A7 and A9–A11 (64MB), or A7 and A9–A12 (128MB)
each set to zero, bit A8 set to one, and bits A0–A6 set to
the desired values.
Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
or A7–A12 (128MB) are reserved for future use and/or
test modes. Test modes and reserved states should not
be used because unknown operation or incompatibil-
ity with future versions may result.
Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram, on page 10. The extended mode
register is programmed via the LOAD MODE REGIS-
COMMAND
COMMAND
The normal operating mode is selected by issuing a
All other combinations of values for A7–A11 (64MB)
The extended mode register controls functions
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
64MB, 128MB (x32, SR)
100-PIN DDR UDIMM
CL = 2
TRANSITIONING DATA
Although not required by the
CL = 2.5
NOP
NOP
T1
T1
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n