MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet - Page 25

• Manufacturer Part Number: MT4VDDT3232UY-6K1
• Description: MODULE DDR 128MB 167MHZ 172-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3232UY-6K1

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 333MT/s
• Package / Case: 172-UDIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 700mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 20: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 26
pdf: 09005aef808da768, source: 09005aef808d2e9a
DD4C16_32x32UG.fm - Rev. D 9/04 EN
BYTE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes Used By Micron
Total Number of Bytes In SPD Device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of Physical Ranks on DIMM
Module Data Width
Module Data Width (Continued)
Module Voltage Interface Levels
SDRAM Cycle Time, (
SDRAM Access From Clock,
2.5)
Module Configuration Type
Refresh Rate/type
Sdram Device Width (Primary DDR SDRAM)
Error-checking Ddr Sdram Data Width
Minimum Clock Delay, Back-to-back Random
Column Access
Burst Lengths Supported
Number Of Banks On Ddr Sdram Device
Cas Latencies Supported
Cs Latency
We Latency
Sdram Module Attributes
Sdram Device Attributes: General
SDRAM Cycle Time,
SDRAM Access from Clock,
2)
SDRAM Cycle Time,
SDRAM Access from CK,
Minimum Row Precharge Time,
Minimum Row Active to Row Active,
Minimum RAS# to CAS# Delay,
Minimum RAS# Pulse Width,
Module Rank Density
Address and Command Setup Time,
(See note 2)
DESCRIPTION
t
t
t
CK (CAS Latency = 2)
CK (CAS Latency = 1.5)
CK) (CAS Latency = 2.5)
t
AC (CAS Latency = 1.5)
t
t
AC (CAS Latency =
AC (CAS Latency =
t
RAS (See note 1)
t
RCD
t
RP (see note 3)
t
IS
t
RRD
Unbuffered/Diff. Clock
ENTRY (VERSION)
15.62µs, 7.8µs/SELF
Fast/Concurrent AP
25
0.75ns (-75Z/-75)
0.75ns (-75Z/-75)
1.0ns (-75Z/-75)
20ns (-75Z/-75)
15ns (-75Z/-75)
20ns (-75Z/-75)
45ns (-75Z/-75)
64MB, 128MB
DDR SDRAM
7.0ns (-75Z)
7.5ns (-75)
SSTL 2.5V
10ns (-75)
0.7ns (-6)
7.5ns (-6)
0.7ns (-6)
0.8ns (-6)
18ns (-6)
12ns (-6)
18ns (-6)
42ns (-6)
6ns (-6)
1 clock
12, 13
2, 4, 8
None
None
2, 2.5
N/A
N/A
128
256
10
32
1
0
8
4
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MB, 128MB (x32, SR)
MT4VDDT1632U
100-PIN DDR UDIMM
0A
A0
2A
2D
A0
80
08
07
0C
01
20
00
04
60
70
75
70
75
00
80
08
00
01
0E
04
0C
01
02
20
C0
75
70
75
00
00
48
50
30
3C
48
50
10
80
©2004 Micron Technology, Inc. All rights reserved.
MT4VDDT3232U
0D
0A
A0
2A
2D
A0
80
08
07
01
20
00
04
60
70
75
70
75
00
82
08
00
01
0E
04
0C
01
02
20
C0
75
70
75
00
00
48
50
30
3C
48
50
20
80