MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet - Page 8

• Manufacturer Part Number: MT4VDDT3232UY-6K1
• Description: MODULE DDR 128MB 167MHZ 172-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3232UY-6K1

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 333MT/s
• Package / Case: 172-UDIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 700mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Burst Length
burst oriented, with the burst length being program-
mable, as shown inFigure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–A9 when the burst length is set to two,
by A2–A9 when the burst length is set to four and by
A3–A9 when the burst length is set to eight.
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. The
programmed burst length applies to both READ and
WRITE bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS
Latency Diagram, on page 9.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9, indicates the oper-
ating frequencies at which each CAS latency setting
can be used.
operation or incompatibility with future versions may
result.
pdf: 09005aef808da768, source: 09005aef808d2e9a
DD4C16_32x32UG.fm - Rev. D 9/04 EN
Read and write accesses to DDR SDRAM devices are
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The
8
* M14 and M13 (BA1 and BA0)
* M13 and M12 (BA1and BA0)
64MB Module Address Bus
128MB Module Address Bus
must be “0, 0” to select the
must be “0, 0” to select the
base mode register (vs. the
base mode register (vs. the
extended mode register).
extended mode register).
Figure 4: Mode Register Definition
0*
14
BA1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
0*
13
13
BA0
BA1
0*
12
12
A12 A11
BA0
Operating Mode
11
11
A11
Operating Mode
10
10
A10
M12 M11
A10
0
0
64MB, 128MB (x32, SR)
-
9
9
A9
A9
0
0
-
8
8
100-PIN DDR UDIMM
A8
A8
M10
0
0
-
7
Diagram
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
M9
M6
0
0
-
CAS Latency BT
CAS Latency BT
0
0
0
0
1
1
1
1
6
6
M8 M7
M5
0
1
-
0
0
1
1
0
0
1
1
5
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
4
©2004 Micron Technology, Inc. All rights reserved.
M6-M0
M3
0
1
Valid
Valid
3
3
-
Burst Length
Burst Length
M2
0
0
0
0
1
1
1
1
2
2
A2 A1 A0
CAS Latency
A2 A1 A0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
1
2.5
2
M0
0
1
0
1
0
1
0
1
0
0
Interleaved
Burst Type
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
Mode Register (Mx)
M3 = 0
Address Bus
Address Bus
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 1
2
4
8