MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet - Page 10

• Manufacturer Part Number: MT4VDDT3232UY-6K1
• Description: MODULE DDR 128MB 167MHZ 172-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3232UY-6K1

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 333MT/s
• Package / Case: 172-UDIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 700mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
DLL Enable/Disable
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time DLL is enabled,
200 clock cycles with CKE HIGH must occur before a
READ command can be issued.
pdf: 09005aef808da768, source: 09005aef808d2e9a
DD4C16_32x32UG.fm - Rev. D 9/04 EN
The extended mode register must be loaded when
The DLL must be enabled for normal operation.
10
NOTE:
128MB Module
64MB Module
1. BA1 and BA0 (E13 and E12 for 64MB or E14 and E13 for
2. QFC# is not supported.
E11
0
14
0
–
BA1 BA0
1
128MB) must be “0, 1” to select the Extended Mode
Register (vs. the base Mode Register).
E10
Figure 6: Extended Mode Register
0
1
BA1 BA0
13
13
0
1
–
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
12
E9
1
12
0
–
A12
11
E8
11
0
A11
–
A11
E7
10
0
–
10
A10
A10
Definition Diagram
Operating Mode
E6 E5
0
–
64MB, 128MB (x32, SR)
9
9
A9
A9
0
–
Operating Mode
8
A8
8
A8
100-PIN DDR UDIMM
E4
0
–
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
E3
0
–
6
6
E2
0
–
5
2
5
©2004 Micron Technology, Inc. All rights reserved.
4
4
E1,
Valid
–
3
E0
3
QFC#
QFC#
2
2
A2 A1 A0
A2 A1 A0
DS
DS
Operating Mode
Normal Operation
All other states reserved
1
1
E1
0
DLL
DLL
0
0
E0
0
1
Extended Mode
Register (Ex)
Extended Mode
Register (Ex)
Drive Strength
Address Bus
Address Bus
Disable
Normal
Enable
DLL