MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet - Page 4

• Manufacturer Part Number: MT4VDDT3232UY-6K1
• Description: MODULE DDR 128MB 167MHZ 172-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3232UY-6K1

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 333MT/s
• Package / Case: 172-UDIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 700mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5:
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables for pin number and symbol information
pdf: 09005aef808da768, source: 09005aef808d2e9a
DD4C16_32x32UG.fm - Rev. D 9/04 EN
1, 3, 6, 7, 9,10, 13, 15, 34, 36,
39, 40, 42, 43, 46, 48, 51, 53,
56, 57, 59, 60, 63, 65, 84, 86,
21 (128MB), 23, 24, 26-29,
89, 90, 92, 93, 96, 98
PIN NUMBERS
54, 62, 87, 95
71-74, 76, 77
4, 12, 37, 45
32, 79, 81
17, 18
31, 78
70
33
49
99
Pin Descriptions
WE#, CAS#, RAS#
DQS0–DQS3
DQ0–DQ31
DM0–DM3
CK0, CK0#
SYMBOL
BA0, BA1
(128MB)
A0–A11
A0–A12
(64MB)
CKE0
SDA
SA0
S0#
Output
Output
Output
Input/
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQ and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank).CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read
and write accesses. Input buffers (excluding CK, CK#, and CKE)
are disabled during POWER-DOWN. Input buffers (excluding
CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after V
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Write Mask. DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
Data I/Os: Data bus.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MB, 128MB (x32, SR)
DESCRIPTION
100-PIN DDR UDIMM
©2004 Micron Technology, Inc. All rights reserved.
DD
is applied.