MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet
MT4VDDT3232UY-6K1
Specifications of MT4VDDT3232UY-6K1
Related parts for MT4VDDT3232UY-6K1
MT4VDDT3232UY-6K1 Summary of contents
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... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 64MB, 128MB (x32, SR) 100-PIN DDR UDIMM MT4VDDT1632U – MT4VDDT3232U – For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 100-Pin DIMM (MO-161) OPTIONS • Package 100-pin DIMM (standard) 100-pin DIMM (lead-free) • ...
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... DENSITY MT4VDDT1632UG-6__ MT4VDDT1632UY-6__ MT4VDDT1632UG-75__ MT4VDDT1632UY-75__ MT4VDDT3232UG-6__ MT4VDDT3232UY-6__ MT4VDDT3232UG-75__ MT4VDDT3232UY-75__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT4VDDT1632UG-75B1 pdf: 09005aef808da768, source: 09005aef808d2e9a DD4C16_32x32UG.fm - Rev. D 9/04 EN CONFIGURATION BANDWIDTH ...
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Table 3: Pin Assignment (100-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 DQ0 DQ11 DQ1 DQS0 17 CK0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables for pin number and symbol information PIN NUMBERS 32, 79, 81 WE#, CAS#, RAS# 17, 18 CK0, CK0 31 (128MB), ...
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... DD Please see note 49, on page 20. V Supply Ground. SS DNU — Do Not Use: This pin is not connected on these modules, but is an assigned pin on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 64MB, 128MB (x32, SR) 100-PIN DDR UDIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... DQ31 REF Standard modules use the following DDR SDRAM devices: MT46V16M8TG (64MB); MT46V32M8TG (128MB) Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (64MB); MT46V32M8P (128MB) 6 64MB, 128MB (x32, SR) 100-PIN DDR UDIMM 120 SPD CK0 DDR SDRAM DDR SDRAMs CK0# X4 DDR SDRAMs ...
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... DDR SDRAM modules use internally config- ured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being program- mable, as shown inFigure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can ...
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Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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TER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 64MB DD DDR SDRAM components only Notes: 1–5, 14, 49; notes appear on pages 17–20; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 13: I Specifications and Conditions – 128MB DD DDR SDRAM components only Notes: 1–5, 14, 49; notes appear on pages 17–20; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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... Table 14: Capacitance (All Modules) Note: 11; notes appear following parameter tables. PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CK, CK#, CKE Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–5, 12–15, 29, 49; notes appear on pages 17–20; 0°C AC CHARACTERISTICS ...
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Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12–15, 29, 49; notes appear on pages 17–20; 0°C AC CHARACTERISTICS PARAMETER ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 ...
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HP min is the lesser of CL minimum and minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not t allowed to be issued ...
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Figure 8: Pull-Down Characteristics 160 140 120 100 0.0 0.5 1 (V) (V) OUT OUT Figure 10: Reduced Output Pull-Down Characteristics 0.0 0.5 1.0 ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 13, Data Validity, and Figure ...
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Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential ...
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Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 20: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 26 BYTE DESCRIPTION 0 Number of SPD Bytes Used By Micron 1 Total Number of Bytes In SPD Device 2 Fundamental Memory Type ...
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... Systems requiring the fast slew rate setup and hold values are supported, provided the faster min- imim slew rate is met The value of RP, RCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef808da768, source: 09005aef808d2e9a DD4C16_32x32UG.fm - Rev. D 9/04 EN ENTRY (VERSION) 0.8ns (- (See 1 ...
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Figure 17: 100-Pin DIMM Dimensions 0.079 (2.00) R (2X) U1 0.118 (3.0) DIA (2X) 0.118 (3.0) PIN 1 0.118 (3.0) No Components This Side of Module PIN 100 NOTE: All dimensions in inches (millimeters); Data Sheet Designation Released (No Mark): ...