MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet - Page 20

• Manufacturer Part Number: MT4VDDT3232UY-6K1
• Description: MODULE DDR 128MB 167MHZ 172-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3232UY-6K1

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 333MT/s
• Package / Case: 172-UDIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 700mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pdf: 09005aef808da768, source: 09005aef808d2e9a
DD4C16_32x32UG.fm - Rev. D 9/04 EN
41. The voltage levels used are derived from a mini-
42. V
43. Random addressing changing and 50 percent of
44. Random addressing changing and 100 percent of
45. CKE must be active (high) during the entire time a
46. I
Figure 10: Reduced Output Pull-Down
160
140
120
100
80
70
60
50
40
30
20
10
80
60
40
20
Figure 8: Pull-Down Characteristics
0
0
0.0
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
data changing at every transfer.
data at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
REF later.
DD
DD
2N specifies the DQ, DQS, and DM to be
and V
DD
0.5
0.5
DD
level and the referenced test load. In
Characteristics
Q must track each other.
1.0
1.0
V
V
V
OUT
OUT
OUT
(V)
(V)
(V)
1.5
1.5
2.0
2.0
Minimum
Minimum
DD
2Q is
2.5
2.5
20
47. Whenever the operating frequency is altered, not
48. Leakage number reflects the worst case leakage
49. When an input signal is HIGH or LOW, it is
50. The -6 speed grade will operate with
-10
-20
-30
-40
-50
-60
-70
-80
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
Figure 11: Reduced Output Pull-Up
0
0.0
0
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
40ns and
frequency.
0.0
Figure 9: Pull-Up Characteristics
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2F is “worst case.”
0.5
0.5
t
64MB, 128MB (x32, SR)
RAS (MAX) = 120,000ns at any slower
DD
Characteristics
DD
2F, I
100-PIN DDR UDIMM
2F except I
DD
1.0
1.0
V
V
DD
DD
2N, and I
Q - V
Q - V
©2004 Micron Technology, Inc. All rights reserved.
OUT
OUT
(V)
(V)
1.5
1.5
DD
DD
2Q specifies the
2Q are similar,
t
RAS (MIN) =
2.0
2.0
Nominal low
Minimum
2.5
2.5