MT46H8M32LFB5-75:A TR Micron Technology Inc, MT46H8M32LFB5-75:A TR Datasheet - Page 67

IC DDR SDRAM 256MBIT 90VFBGA

MT46H8M32LFB5-75:A TR

Manufacturer Part Number
MT46H8M32LFB5-75:A TR
Description
IC DDR SDRAM 256MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT46H8M32LFB5-75:A TR

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (8Mx32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 38:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ and DQS collectively
DQ (Last data valid)
DQ (Last data valid)
DQM0/DQM1/DQM2/DQM3
Data Output Timing –
Notes:
CK#
DQ
DQ
DQ
DQ
DQ
DQ
CK
2
2
2
2
2
2
2
2
2
2
6
1. DQ transitioning after DQS transitions defines the
2. Byte 0 is DQ[7:0]; byte 1 is DQ[15:8]; byte 2 is DQ[23:16]; byte 3 is DQ[31:24].
3.
4.
5.
6. The data valid window is derived for each DQS transition and is
T1
t
DQS transition and ends with the last valid DQ transition.
t
t
DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
QH is derived from
HP is the lesser of
t HP
5
t
DQSQ,
t HP
5
t DQSQ
t QH
t
T2
CL or
4
t
Data valid
t
QH, and Data Valid Window (x32)
3
HP:
window
T2
T2
T2
t HP
t
t
QH =
5
CH clock transition collectively when a bank is active.
t DQSQ
T2n
67
t QH
Data valid
t
HP -
4
window
3
t HP
T2n
T2n
T2n
5
t
QHS.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
256Mb: x16, x32 Mobile DDR SDRAM
t DQSQ
t QH
t HP
4
Data valid
window
3
5
T3
T3
T3
T3n
t
DQSQ window.
t DQSQ
t HP
t QH
5
4
Data valid
3
window
T4
T3n
T3n
T3n
©2005 Micron Technology, Inc. All rights reserved.
t
QH -
Timing Diagrams
t
DQSQ.

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